From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F09EC43612 for ; Wed, 2 Jan 2019 14:01:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 12361218CD for ; Wed, 2 Jan 2019 14:01:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730110AbfABOB3 (ORCPT ); Wed, 2 Jan 2019 09:01:29 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:16727 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730013AbfABOBJ (ORCPT ); Wed, 2 Jan 2019 09:01:09 -0500 X-UUID: d23b80df51ea4817aefa0476a1ad62b8-20190102 X-UUID: d23b80df51ea4817aefa0476a1ad62b8-20190102 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 244234613; Wed, 02 Jan 2019 22:00:58 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs02n2.mediatek.inc (172.21.101.101) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 2 Jan 2019 22:00:56 +0800 Received: from mtkslt205.mediatek.inc (10.21.15.75) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 2 Jan 2019 22:00:56 +0800 From: Henry Chen To: Viresh Kumar , Stephen Boyd , Rob Herring , Matthias Brugger , Ulf Hansson CC: Mark Rutland , Fan Chen , Weiyi Lu , James Liao , Kees Cook , , , , , , Henry Chen Subject: [RFC PATCH 1/7] dt-bindings: soc: Add DVFSRC driver bindings Date: Wed, 2 Jan 2019 21:43:58 +0800 Message-ID: <1546436644-19234-2-git-send-email-henryc.chen@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1546436644-19234-1-git-send-email-henryc.chen@mediatek.com> References: <1546436644-19234-1-git-send-email-henryc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain X-TM-SNTS-SMTP: AAA9A09DA6C739B431FC5C1F94D631C049D342526B5E35733391914CED7F060D2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Document the binding for enabling DVFSRC on MediaTek SoC. Signed-off-by: Henry Chen --- .../devicetree/bindings/soc/mediatek/dvfsrc.txt | 26 ++++++++++++++++++++++ include/dt-bindings/soc/mtk,dvfsrc.h | 18 +++++++++++++++ 2 files changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt create mode 100644 include/dt-bindings/soc/mtk,dvfsrc.h diff --git a/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt new file mode 100644 index 0000000..402c885 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mediatek/dvfsrc.txt @@ -0,0 +1,26 @@ +MediaTek DVFSRC Driver + +The Dynamic Voltage and Frequency Scaling Resource Collector (DVFSRC) is a +HW module which is used to collect all the requests from both software and +hardware and turn into the decision of minimum operating voltage and minimum +DRAM frequency to fulfill those requests. + +Required Properties: +- compatible: Should be one of the following + - "mediatek,mt8183-dvfsrc": For MT8183 SoC +- reg: Address range of the DVFSRC unit +- dram_type: Refer to for the + different dram type support. +- clock-names: Must include the following entries: + "dvfsrc": DVFSRC module clock +- clocks: Must contain an entry for each entry in clock-names. + +Example: + + dvfsrc_top@10012000 { + compatible = "mediatek,mt8183-dvfsrc"; + reg = <0 0x10012000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_DVFSRC>; + clock-names = "dvfsrc"; + dram_type = ; + }; diff --git a/include/dt-bindings/soc/mtk,dvfsrc.h b/include/dt-bindings/soc/mtk,dvfsrc.h new file mode 100644 index 0000000..60b3497 --- /dev/null +++ b/include/dt-bindings/soc/mtk,dvfsrc.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 + * + * Copyright (c) 2018 MediaTek Inc. + */ + +#ifndef _DT_BINDINGS_POWER_MTK_DVFSRC_H +#define _DT_BINDINGS_POWER_MTK_DVFSRC_H + +#define MT8183_DVFSRC_OPP_LP4 0 +#define MT8183_DVFSRC_OPP_LP4X 1 +#define MT8183_DVFSRC_OPP_LP3 2 + +#define MT8183_DVFSRC_LEVEL_1 1 +#define MT8183_DVFSRC_LEVEL_2 2 +#define MT8183_DVFSRC_LEVEL_3 3 +#define MT8183_DVFSRC_LEVEL_4 4 + +#endif /* _DT_BINDINGS_POWER_MTK_DVFSRC_H */ -- 1.9.1