From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0F2EC10F13 for ; Thu, 11 Apr 2019 10:57:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B9F552133D for ; Thu, 11 Apr 2019 10:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726823AbfDKK5T (ORCPT ); Thu, 11 Apr 2019 06:57:19 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:56463 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726215AbfDKK5T (ORCPT ); Thu, 11 Apr 2019 06:57:19 -0400 X-UUID: 474c8febed2d445b897e13ac48bd3950-20190411 X-UUID: 474c8febed2d445b897e13ac48bd3950-20190411 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1554356599; Thu, 11 Apr 2019 18:57:11 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n2.mediatek.inc (172.21.101.79) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 11 Apr 2019 18:57:09 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 11 Apr 2019 18:57:09 +0800 Message-ID: <1554980229.27008.4.camel@mtksdaap41> Subject: Re: [PATCH v2 14/25] drm/medaitek: add layer_nr for ovl private data From: CK Hu To: CC: , , , , , , , , , , , Date: Thu, 11 Apr 2019 18:57:09 +0800 In-Reply-To: <1553667561-25447-15-git-send-email-yongqiang.niu@mediatek.com> References: <1553667561-25447-1-git-send-email-yongqiang.niu@mediatek.com> <1553667561-25447-15-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 4A29E8A5A2798424AD776A0006797D6F7DEB842A90BCB0FA8FF5EA40D0713D4C2000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Wed, 2019-03-27 at 14:19 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add layer_nr for ovl private data > ovl_2l almost same with with ovl hardware, except the > layer number for ovl_2l is 2 and ovl is 4. > this patch is a preparation for ovl-2l and > ovl share the same driver. Reviewed-by: CK Hu > > Signed-off-by: Yongqiang Niu > --- > drivers/gpu/drm/mediatek/mtk_disp_ovl.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > index afb313c..a0ab760 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_ovl.c > @@ -60,6 +60,7 @@ > struct mtk_disp_ovl_data { > unsigned int addr; > unsigned int gmc_bits; > + unsigned int layer_nr; > bool fmt_rgb565_is_0; > }; > > @@ -137,7 +138,9 @@ static void mtk_ovl_config(struct mtk_ddp_comp *comp, unsigned int w, > > static unsigned int mtk_ovl_layer_nr(struct mtk_ddp_comp *comp) > { > - return 4; > + struct mtk_disp_ovl *ovl = comp_to_ovl(comp); > + > + return ovl->data->layer_nr; > } > > static void mtk_ovl_layer_on(struct mtk_ddp_comp *comp, unsigned int idx) > @@ -342,12 +345,14 @@ static int mtk_disp_ovl_remove(struct platform_device *pdev) > static const struct mtk_disp_ovl_data mt2701_ovl_driver_data = { > .addr = DISP_REG_OVL_ADDR_MT2701, > .gmc_bits = 8, > + .layer_nr = 4, > .fmt_rgb565_is_0 = false, > }; > > static const struct mtk_disp_ovl_data mt8173_ovl_driver_data = { > .addr = DISP_REG_OVL_ADDR_MT8173, > .gmc_bits = 8, > + .layer_nr = 4, > .fmt_rgb565_is_0 = true, > }; >