From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19DE1C10F03 for ; Tue, 23 Apr 2019 15:25:24 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id D5D39206BA for ; Tue, 23 Apr 2019 15:25:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728421AbfDWPZV (ORCPT ); Tue, 23 Apr 2019 11:25:21 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:8407 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726655AbfDWPZV (ORCPT ); Tue, 23 Apr 2019 11:25:21 -0400 X-UUID: 7d581653d7544a2da7c7521ea0da047e-20190423 X-UUID: 7d581653d7544a2da7c7521ea0da047e-20190423 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 776834800; Tue, 23 Apr 2019 23:25:17 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Tue, 23 Apr 2019 23:25:09 +0800 Received: from [172.21.77.33] (172.21.77.33) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Tue, 23 Apr 2019 23:25:03 +0800 Message-ID: <1556033102.20906.4.camel@mtkswgap22> Subject: Re: [PATCH v4 09/12] soc: mediatek: cmdq: add polling function From: Dennis-YC Hsieh To: Bibby Hsieh CC: Jassi Brar , Matthias Brugger , Rob Herring , CK HU , Daniel Kurtz , Sascha Hauer , , , , , , "Sascha Hauer" , Philipp Zabel , Nicolas Boichat , YT Shen , Daoyuan Huang , Jiaguang Zhang , Houlong Wei , , , Frederic Chen Date: Tue, 23 Apr 2019 23:25:02 +0800 In-Reply-To: <20190415125833.38704-10-bibby.hsieh@mediatek.com> References: <20190415125833.38704-1-bibby.hsieh@mediatek.com> <20190415125833.38704-10-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.2.3-0ubuntu6 Content-Transfer-Encoding: 7bit MIME-Version: 1.0 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Bibby, On Mon, 2019-04-15 at 20:58 +0800, Bibby Hsieh wrote: > add polling function in cmdq helper functions > > Signed-off-by: Bibby Hsieh > --- > drivers/soc/mediatek/mtk-cmdq-helper.c | 30 ++++++++++++++++++++++++ > include/linux/mailbox/mtk-cmdq-mailbox.h | 1 + > include/linux/soc/mediatek/mtk-cmdq.h | 15 ++++++++++++ > 3 files changed, 46 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c > index d3873ab21db3..80856b8c2385 100644 > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c > @@ -231,6 +231,36 @@ int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event) > } > EXPORT_SYMBOL(cmdq_pkt_clear_event); > > +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, > + u16 offset, u32 value, u32 mask) > +{ > + int err; > + > + if (mask != 0xffffffff) { > + err = cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(~mask), > + CMDQ_GET_ARG_B(~mask), > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_CODE_MASK); > + > + if (err != 0) > + return err; > + } > + offset = offset | 0x1; Does this "or" operation make gce use mask? If it does, maybe it should move into brace? Regards, Dennis > + > + return cmdq_pkt_append_command(pkt, CMDQ_GET_ARG_C(value), > + CMDQ_GET_ARG_B(value), > + offset, subsys, > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_IMMEDIATE_VALUE, > + CMDQ_CODE_POLL); > +} > +EXPORT_SYMBOL(cmdq_pkt_poll); > + > static int cmdq_pkt_finalize(struct cmdq_pkt *pkt) > { > int err; > diff --git a/include/linux/mailbox/mtk-cmdq-mailbox.h b/include/linux/mailbox/mtk-cmdq-mailbox.h > index f21801d32a3a..1dfd5ed5c8c5 100644 > --- a/include/linux/mailbox/mtk-cmdq-mailbox.h > +++ b/include/linux/mailbox/mtk-cmdq-mailbox.h > @@ -46,6 +46,7 @@ > enum cmdq_code { > CMDQ_CODE_MASK = 0x02, > CMDQ_CODE_WRITE = 0x04, > + CMDQ_CODE_POLL = 0x08, > CMDQ_CODE_JUMP = 0x10, > CMDQ_CODE_WFE = 0x20, > CMDQ_CODE_EOC = 0x40, > diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h > index 52f69c8db8de..0651a0bffa54 100644 > --- a/include/linux/soc/mediatek/mtk-cmdq.h > +++ b/include/linux/soc/mediatek/mtk-cmdq.h > @@ -99,6 +99,21 @@ int cmdq_pkt_wfe(struct cmdq_pkt *pkt, u16 event); > */ > int cmdq_pkt_clear_event(struct cmdq_pkt *pkt, u16 event); > > +/** > + * cmdq_pkt_poll() - Append polling command to the CMDQ packet, ask GCE to > + * execute an instruction that wait for a specified hardware > + * register to check for the value. All GCE hardware > + * threads will be blocked by this instruction. > + * @pkt: the CMDQ packet > + * @subsys: the CMDQ sub system code > + * @offset: register offset from CMDQ sub system > + * @value: the specified target register value > + * @mask: the specified target register mask > + * > + * Return: 0 for success; else the error code is returned > + */ > +int cmdq_pkt_poll(struct cmdq_pkt *pkt, u8 subsys, > + u16 offset, u32 value, u32 mask); > /** > * cmdq_pkt_flush_async() - trigger CMDQ to asynchronously execute the CMDQ > * packet and call back at the end of done packet