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From: kan.liang@linux.intel.com
To: mingo@kernel.org, acme@redhat.com, peterz@infradead.org,
	vincent.weaver@maine.edu, linux-kernel@vger.kernel.org
Cc: alexander.shishkin@linux.intel.com, ak@linux.intel.com,
	jolsa@redhat.com, eranian@google.com,
	Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V3 5/5] perf regs x86: Use PERF_REG_EXTENDED_MASK
Date: Tue, 28 May 2019 15:08:34 -0700	[thread overview]
Message-ID: <1559081314-9714-5-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1559081314-9714-1-git-send-email-kan.liang@linux.intel.com>

From: Kan Liang <kan.liang@linux.intel.com>

Use the macro defined in kernel ABI header to replace the local name.

No functional change.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---

Changes since V2:
- Rename PERF_REG_NON_GENERIC_MASK to PERF_REG_EXTENDED_MASK

 tools/arch/x86/include/uapi/asm/perf_regs.h | 3 +++
 tools/perf/arch/x86/include/perf_regs.h     | 1 -
 tools/perf/arch/x86/util/perf_regs.c        | 4 ++--
 3 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/tools/arch/x86/include/uapi/asm/perf_regs.h b/tools/arch/x86/include/uapi/asm/perf_regs.h
index ac67bbe..7c9d2bb 100644
--- a/tools/arch/x86/include/uapi/asm/perf_regs.h
+++ b/tools/arch/x86/include/uapi/asm/perf_regs.h
@@ -52,4 +52,7 @@ enum perf_event_x86_regs {
 	/* These include both GPRs and XMMX registers */
 	PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2,
 };
+
+#define PERF_REG_EXTENDED_MASK	(~((1ULL << PERF_REG_X86_XMM0) - 1))
+
 #endif /* _ASM_X86_PERF_REGS_H */
diff --git a/tools/perf/arch/x86/include/perf_regs.h b/tools/perf/arch/x86/include/perf_regs.h
index b7cd91a..b732133 100644
--- a/tools/perf/arch/x86/include/perf_regs.h
+++ b/tools/perf/arch/x86/include/perf_regs.h
@@ -9,7 +9,6 @@
 void perf_regs_load(u64 *regs);
 
 #define PERF_REGS_MAX PERF_REG_X86_XMM_MAX
-#define PERF_XMM_REGS_MASK	(~((1ULL << PERF_REG_X86_XMM0) - 1))
 #ifndef HAVE_ARCH_X86_64_SUPPORT
 #define PERF_REGS_MASK ((1ULL << PERF_REG_X86_32_MAX) - 1)
 #define PERF_SAMPLE_REGS_ABI PERF_SAMPLE_REGS_ABI_32
diff --git a/tools/perf/arch/x86/util/perf_regs.c b/tools/perf/arch/x86/util/perf_regs.c
index 7886ca5..3666c00 100644
--- a/tools/perf/arch/x86/util/perf_regs.c
+++ b/tools/perf/arch/x86/util/perf_regs.c
@@ -277,7 +277,7 @@ uint64_t arch__intr_reg_mask(void)
 		.type			= PERF_TYPE_HARDWARE,
 		.config			= PERF_COUNT_HW_CPU_CYCLES,
 		.sample_type		= PERF_SAMPLE_REGS_INTR,
-		.sample_regs_intr	= PERF_XMM_REGS_MASK,
+		.sample_regs_intr	= PERF_REG_EXTENDED_MASK,
 		.precise_ip		= 1,
 		.disabled 		= 1,
 		.exclude_kernel		= 1,
@@ -293,7 +293,7 @@ uint64_t arch__intr_reg_mask(void)
 	fd = sys_perf_event_open(&attr, 0, -1, -1, 0);
 	if (fd != -1) {
 		close(fd);
-		return (PERF_XMM_REGS_MASK | PERF_REGS_MASK);
+		return (PERF_REG_EXTENDED_MASK | PERF_REGS_MASK);
 	}
 
 	return PERF_REGS_MASK;
-- 
2.7.4


  parent reply	other threads:[~2019-05-28 22:09 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-28 22:08 [PATCH V3 1/5] perf: Disable extended registers for non-support PMUs kan.liang
2019-05-28 22:08 ` [PATCH V3 2/5] perf/x86/regs: Check reserved bits kan.liang
2019-06-25  8:20   ` [tip:perf/urgent] " tip-bot for Kan Liang
2019-05-28 22:08 ` [PATCH V3 3/5] perf/x86: Clean up PEBS_XMM_REGS kan.liang
2019-06-25  8:21   ` [tip:perf/urgent] " tip-bot for Kan Liang
2019-05-28 22:08 ` [PATCH V3 4/5] perf/x86: Clean up pebs_no_xmm_regs kan.liang
2019-06-25  8:22   ` [tip:perf/urgent] perf/x86: Remove pmu->pebs_no_xmm_regs tip-bot for Kan Liang
2019-05-28 22:08 ` kan.liang [this message]
2019-06-25  8:22   ` [tip:perf/urgent] perf/x86/regs: Use PERF_REG_EXTENDED_MASK tip-bot for Kan Liang
2019-06-20 12:24 ` [PATCH V3 1/5] perf: Disable extended registers for non-support PMUs Peter Zijlstra
2019-06-25  8:19 ` [tip:perf/urgent] perf/x86: Disable extended registers for non-supported PMUs tip-bot for Kan Liang

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