From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46485C28CC5 for ; Mon, 3 Jun 2019 02:19:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 245E227AD1 for ; Mon, 3 Jun 2019 02:19:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726964AbfFCCTr (ORCPT ); Sun, 2 Jun 2019 22:19:47 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:48089 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726305AbfFCCTq (ORCPT ); Sun, 2 Jun 2019 22:19:46 -0400 X-UUID: 2a27758f1ed445d3ae430e40fa8cbcf4-20190603 X-UUID: 2a27758f1ed445d3ae430e40fa8cbcf4-20190603 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 1566463222; Mon, 03 Jun 2019 10:19:39 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by MTKMBS33N2.mediatek.inc (172.27.4.76) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 3 Jun 2019 10:19:36 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 3 Jun 2019 10:19:34 +0800 Message-ID: <1559528374.32185.4.camel@mtksdaap41> Subject: Re: [v4 3/7] drm/mediatek: add dsi reg commit disable control From: CK Hu To: Jitao Shi CC: Rob Herring , Pawel Moll , "Mark Rutland" , Ian Campbell , , David Airlie , Matthias Brugger , "Thierry Reding" , Ajay Kumar , "Inki Dae" , Rahul Sharma , "Sean Paul" , Vincent Palatin , "Andy Yan" , Philipp Zabel , Russell King , , , , , , , Sascha Hauer , , , , , Date: Mon, 3 Jun 2019 10:19:34 +0800 In-Reply-To: <20190601092615.67917-4-jitao.shi@mediatek.com> References: <20190601092615.67917-1-jitao.shi@mediatek.com> <20190601092615.67917-4-jitao.shi@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Jitao: On Sat, 2019-06-01 at 17:26 +0800, Jitao Shi wrote: > New DSI IP has shadow register and working reg. The register > values are writen to shadow register. And then trigger with > commit reg, the register values will be moved working register. > > This fucntion is defualt on. But this driver doesn't use this > function. So add the disable control. Reviewed-by: CK Hu > > Signed-off-by: Jitao Shi > --- > drivers/gpu/drm/mediatek/mtk_dsi.c | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c > index a48db056df6c..eea47294079e 100644 > --- a/drivers/gpu/drm/mediatek/mtk_dsi.c > +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c > @@ -131,6 +131,10 @@ > #define VM_CMD_EN BIT(0) > #define TS_VFP_EN BIT(5) > > +#define DSI_SHADOW_DEBUG 0x190U > +#define FORCE_COMMIT BIT(0) > +#define BYPASS_SHADOW BIT(1) > + > #define CONFIG (0xff << 0) > #define SHORT_PACKET 0 > #define LONG_PACKET 2 > @@ -157,6 +161,7 @@ struct phy; > > struct mtk_dsi_driver_data { > const u32 reg_cmdq_off; > + bool has_shadow_ctl; > }; > > struct mtk_dsi { > @@ -594,6 +599,11 @@ static int mtk_dsi_poweron(struct mtk_dsi *dsi) > } > > mtk_dsi_enable(dsi); > + > + if (dsi->driver_data->has_shadow_ctl) > + writel(FORCE_COMMIT | BYPASS_SHADOW, > + dsi->regs + DSI_SHADOW_DEBUG); > + > mtk_dsi_reset_engine(dsi); > mtk_dsi_phy_timconfig(dsi); >