From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.5 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,USER_AGENT_SANE_2 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C010C0650E for ; Mon, 1 Jul 2019 08:07:51 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 5A176208C4 for ; Mon, 1 Jul 2019 08:07:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727790AbfGAIHu (ORCPT ); Mon, 1 Jul 2019 04:07:50 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:55576 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726402AbfGAIHt (ORCPT ); Mon, 1 Jul 2019 04:07:49 -0400 X-UUID: 45e0ed03ee754ba388e3c4726bc25420-20190701 X-UUID: 45e0ed03ee754ba388e3c4726bc25420-20190701 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 633325689; Mon, 01 Jul 2019 16:07:28 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Mon, 1 Jul 2019 16:07:26 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Mon, 1 Jul 2019 16:07:26 +0800 Message-ID: <1561968446.3524.1.camel@mtksdaap41> Subject: Re: [PATCH v10 11/12] soc: mediatek: cmdq: add cmdq_dev_get_client_reg function From: CK Hu To: Bibby Hsieh CC: Jassi Brar , Matthias Brugger , Rob Herring , Daniel Kurtz , Sascha Hauer , , , , , , Sascha Hauer , "Philipp Zabel" , Nicolas Boichat , "YT Shen" , Daoyuan Huang , Jiaguang Zhang , Dennis-YC Hsieh , Houlong Wei , Date: Mon, 1 Jul 2019 16:07:26 +0800 In-Reply-To: <20190701074842.15401-12-bibby.hsieh@mediatek.com> References: <20190701074842.15401-1-bibby.hsieh@mediatek.com> <20190701074842.15401-12-bibby.hsieh@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Bibby: On Mon, 2019-07-01 at 15:48 +0800, Bibby Hsieh wrote: > GCE cannot know the register base address, this function > can help cmdq client to get the cmdq_client_reg structure. > Reviewed-by: CK Hu > Signed-off-by: Bibby Hsieh > --- > drivers/soc/mediatek/mtk-cmdq-helper.c | 28 ++++++++++++++++++++++++++ > include/linux/soc/mediatek/mtk-cmdq.h | 21 +++++++++++++++++++ > 2 files changed, 49 insertions(+) > > diff --git a/drivers/soc/mediatek/mtk-cmdq-helper.c b/drivers/soc/mediatek/mtk-cmdq-helper.c > index 70ad4d806fac..ad52ac3ccfbb 100644 > --- a/drivers/soc/mediatek/mtk-cmdq-helper.c > +++ b/drivers/soc/mediatek/mtk-cmdq-helper.c > @@ -27,6 +27,34 @@ struct cmdq_instruction { > u8 op; > }; > > +int cmdq_dev_get_client_reg(struct device *dev, > + struct cmdq_client_reg *client_reg, int idx) > +{ > + struct of_phandle_args spec; > + int err; > + > + if (!client_reg) > + return -ENOENT; > + > + err = of_parse_phandle_with_args(dev->of_node, "mediatek,gce-client-reg", > + "#subsys-cells", idx, &spec); > + if (err < 0) { > + dev_err(dev, > + "error %d can't parse gce-client-reg property (%d)", > + err, idx); > + > + return err; > + } > + > + client_reg->subsys = spec.args[0]; > + client_reg->offset = spec.args[1]; > + client_reg->size = spec.args[2]; > + of_node_put(spec.np); > + > + return 0; > +} > +EXPORT_SYMBOL(cmdq_dev_get_client_reg); > + > static void cmdq_client_timeout(struct timer_list *t) > { > struct cmdq_client *client = from_timer(client, t, timer); > diff --git a/include/linux/soc/mediatek/mtk-cmdq.h b/include/linux/soc/mediatek/mtk-cmdq.h > index a345870a6d10..be402c4c740e 100644 > --- a/include/linux/soc/mediatek/mtk-cmdq.h > +++ b/include/linux/soc/mediatek/mtk-cmdq.h > @@ -15,6 +15,12 @@ > > struct cmdq_pkt; > > +struct cmdq_client_reg { > + u8 subsys; > + u16 offset; > + u16 size; > +}; > + > struct cmdq_client { > spinlock_t lock; > u32 pkt_cnt; > @@ -142,4 +148,19 @@ int cmdq_pkt_flush_async(struct cmdq_pkt *pkt, cmdq_async_flush_cb cb, > */ > int cmdq_pkt_flush(struct cmdq_pkt *pkt); > > +/** > + * cmdq_dev_get_client_reg() - parse cmdq client reg from the device > + * node of CMDQ client > + * @dev: device of CMDQ mailbox clienti > + * @client_reg: CMDQ client reg pointer > + * @idx: the index of desired reg > + * > + * Return: 0 for success; else the error code is returned > + * > + * Help CMDQ client pasing the cmdq client reg > + * from the device node of CMDQ client. > + */ > +int cmdq_dev_get_client_reg(struct device *dev, > + struct cmdq_client_reg *client_reg, int idx); > + > #endif /* __MTK_CMDQ_H__ */