linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
From: Wei Wang <wei.w.wang@intel.com>
To: linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	ak@linux.intel.com, peterz@infradead.org, pbonzini@redhat.com
Cc: kan.liang@intel.com, mingo@redhat.com, rkrcmar@redhat.com,
	like.xu@intel.com, wei.w.wang@intel.com, jannh@google.com,
	arei.gonglei@huawei.com, jmattson@google.com
Subject: [PATCH v8 11/14] perf/x86: save/restore LBR_SELECT on vcpu switching
Date: Tue,  6 Aug 2019 15:16:11 +0800	[thread overview]
Message-ID: <1565075774-26671-12-git-send-email-wei.w.wang@intel.com> (raw)
In-Reply-To: <1565075774-26671-1-git-send-email-wei.w.wang@intel.com>

The regular host lbr perf event doesn't save/restore the LBR_SELECT msr
during a thread context switching, because the LBR_SELECT value is
generated from attr.branch_sample_type and already stored in
event->hw.branch_reg (please see intel_pmu_setup_hw_filter), which
doesn't get lost during thread context switching.

The attr.branch_sample_type for the vcpu lbr event is deliberately set
to the user call stack mode to enable the perf core to save/restore the
lbr related msrs on vcpu switching. So the attr.branch_sample_type
essentially doesn't represent what the guest pmu driver will write to
LBR_SELECT. Meanwhile, the host lbr driver doesn't configure the lbr msrs,
including the LBR_SELECT msr, for the vcpu thread case, as the pmu driver
inside the vcpu will do that.

So for the vcpu case, add the LBR_SELECT save/restore to ensure what the
guest writes to the LBR_SELECT msr doesn't get lost during the vcpu context
switching.

Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Kan Liang <kan.liang@intel.com>
Signed-off-by: Wei Wang <wei.w.wang@intel.com>
---
 arch/x86/events/intel/lbr.c  | 7 +++++++
 arch/x86/events/perf_event.h | 1 +
 2 files changed, 8 insertions(+)

diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index a0f3686..236f8352 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -390,6 +390,9 @@ static void __intel_pmu_lbr_restore(struct x86_perf_task_context *task_ctx)
 
 	wrmsrl(x86_pmu.lbr_tos, tos);
 	task_ctx->lbr_stack_state = LBR_NONE;
+
+	if (cpuc->vcpu_lbr)
+		wrmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel);
 }
 
 static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
@@ -416,6 +419,10 @@ static void __intel_pmu_lbr_save(struct x86_perf_task_context *task_ctx)
 		if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_INFO)
 			rdmsrl(MSR_LBR_INFO_0 + lbr_idx, task_ctx->lbr_info[i]);
 	}
+
+	if (cpuc->vcpu_lbr)
+		rdmsrl(MSR_LBR_SELECT, task_ctx->lbr_sel);
+
 	task_ctx->valid_lbrs = i;
 	task_ctx->tos = tos;
 	task_ctx->lbr_stack_state = LBR_VALID;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index 8b90a25..0b2f660 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -699,6 +699,7 @@ struct x86_perf_task_context {
 	u64 lbr_from[MAX_LBR_ENTRIES];
 	u64 lbr_to[MAX_LBR_ENTRIES];
 	u64 lbr_info[MAX_LBR_ENTRIES];
+	u64 lbr_sel;
 	int tos;
 	int valid_lbrs;
 	int lbr_callstack_users;
-- 
2.7.4


  parent reply	other threads:[~2019-08-06  8:06 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-06  7:16 [PATCH v8 00/14] Guest LBR Enabling Wei Wang
2019-08-06  7:16 ` [PATCH v8 01/14] perf/x86: fix the variable type of the lbr msrs Wei Wang
2019-08-06  7:16 ` [PATCH v8 02/14] perf/x86: add a function to get the addresses of the lbr stack msrs Wei Wang
2019-08-06  7:16 ` [PATCH v8 03/14] KVM/x86: KVM_CAP_X86_GUEST_LBR Wei Wang
2019-08-06  7:16 ` [PATCH v8 04/14] KVM/x86: intel_pmu_lbr_enable Wei Wang
2019-08-06  7:16 ` [PATCH v8 05/14] KVM/x86/vPMU: tweak kvm_pmu_get_msr Wei Wang
2019-08-06  7:16 ` [PATCH v8 06/14] KVM/x86: expose MSR_IA32_PERF_CAPABILITIES to the guest Wei Wang
2019-08-06  7:16 ` [PATCH v8 07/14] perf/x86: support to create a perf event without counter allocation Wei Wang
2019-08-06  7:16 ` [PATCH v8 08/14] perf/core: set the event->owner before event_init Wei Wang
2019-08-06  7:16 ` [PATCH v8 09/14] KVM/x86/vPMU: APIs to create/free lbr perf event for a vcpu thread Wei Wang
2019-08-06  7:16 ` [PATCH v8 10/14] perf/x86/lbr: don't share lbr for the vcpu usage case Wei Wang
2019-08-06  7:16 ` Wei Wang [this message]
2019-08-06  7:16 ` [PATCH v8 12/14] KVM/x86/lbr: lbr emulation Wei Wang
2019-12-10 23:37   ` Sean Christopherson
2019-08-06  7:16 ` [PATCH v8 13/14] KVM/x86/vPMU: check the lbr feature before entering guest Wei Wang
2019-08-07  6:02   ` Wei Wang
2019-08-06  7:16 ` [PATCH v8 14/14] KVM/x86: remove the common handling of the debugctl msr Wei Wang
2019-09-06  8:50 ` [PATCH v8 00/14] Guest LBR Enabling Wang, Wei W
2020-01-30 20:14 ` Eduardo Habkost
2020-01-31  1:01   ` Wang, Wei W

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=1565075774-26671-12-git-send-email-wei.w.wang@intel.com \
    --to=wei.w.wang@intel.com \
    --cc=ak@linux.intel.com \
    --cc=arei.gonglei@huawei.com \
    --cc=jannh@google.com \
    --cc=jmattson@google.com \
    --cc=kan.liang@intel.com \
    --cc=kvm@vger.kernel.org \
    --cc=like.xu@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=mingo@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peterz@infradead.org \
    --cc=rkrcmar@redhat.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).