Re: [PATCH] clk: ingenic/jz4740: Fix "pll half" divider not read/written properly

[Paul Cercueil <paul@crapouillou.net>]

Le jeu. 8 août 2019 à 6:08, Stephen Boyd <sboyd@kernel.org> a écrit :
> Quoting Paul Cercueil (2019-08-07 16:28:10)
>> 
>> 
>>  Le mer. 7 août 2019 à 23:33, Stephen Boyd <sboyd@kernel.org> a 
>> écrit
>>  :
>>  > Quoting Paul Cercueil (2019-07-01 04:36:06)
>>  >>  The code was setting the bit 21 of the CPCCR register to use a
>>  >> divider
>>  >>  of 2 for the "pll half" clock, and clearing the bit to use a 
>> divider
>>  >>  of 1.
>>  >>
>>  >>  This is the opposite of how this register field works: a 
>> cleared bit
>>  >>  means that the /2 divider is used, and a set bit means that the
>>  >> divider
>>  >>  is 1.
>>  >>
>>  >>  Restore the correct behaviour using the newly introduced 
>> .div_table
>>  >>  field.
>>  >>
>>  >>  Signed-off-by: Paul Cercueil <paul@crapouillou.net>
>>  >>  ---
>>  >
>>  > Applied to clk-next. Does this need a fixes tag?
>> 
>>  It depends on commit a9fa2893fcc6 ("clk: ingenic: Add support for
>>  divider tables") which was sent without a fixes tag, so it'd be
>>  a bit difficult. Probably not worth the trouble.
>> 
> 
> Does it need to go in as a fix for this -rc series then? Or is it not
> causing issues for you so it's ok to wait until next merge window?

It can wait for the next merge window, yes.

-Paul