From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS, UNPARSEABLE_RELAY,URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 867B7C3A59D for ; Thu, 22 Aug 2019 08:12:30 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6545C20870 for ; Thu, 22 Aug 2019 08:12:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732139AbfHVIM3 (ORCPT ); Thu, 22 Aug 2019 04:12:29 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:4560 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731361AbfHVIM1 (ORCPT ); Thu, 22 Aug 2019 04:12:27 -0400 X-UUID: 148adf214d5e41aeb732a3567d7658e1-20190822 X-UUID: 148adf214d5e41aeb732a3567d7658e1-20190822 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 505389812; Thu, 22 Aug 2019 16:12:21 +0800 Received: from mtkcas08.mediatek.inc (172.21.101.126) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 16:12:15 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas08.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 16:12:15 +0800 Message-ID: <1566461540.16302.4.camel@mtksdaap41> Subject: Re: [PATCH v5 08/13] dt-bindings: pwm: update bindings for MT7628 SoC From: Yingjoe Chen To: Sam Shih CC: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding , , Ryder Lee , , , , "John Crispin" Date: Thu, 22 Aug 2019 16:12:20 +0800 In-Reply-To: <1566457123-20791-9-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> <1566457123-20791-9-git-send-email-sam.shih@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 3BD61D47ACABA7964220A1B0223F5209B3AA948622B67FF3DAA9B078EE5B90732000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 2019-08-22 at 14:58 +0800, Sam Shih wrote: > This updates bindings for MT7628 pwm controller. > > Signed-off-by: Sam Shih > --- > Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt > index ea95b490a913..93980e3da261 100644 > --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt > +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt > @@ -21,6 +21,10 @@ Required properties: > See pinctrl/pinctrl-bindings.txt for details of the property values. > - num-pwms: the number of PWM channels. > + > + Optional properties: > + - clock-frequency: fix clock frequency, this is only used in MT7628 SoC > + for period calculation. This SoC has no complex clock tree. I'm sorry if this has been discussed before. Would it be simpler if you just provide a fixed-clock as clock in device tree? This way you don't need this optional properties and don't need to special handle it in driver code. After all, the hw is still connected to a simple clock tree. Joe.C