From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, MENTIONS_GIT_HOSTING,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY, URIBL_BLOCKED,USER_AGENT_SANE_2 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B5A65ECE58D for ; Wed, 9 Oct 2019 09:18:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 98A7C21848 for ; Wed, 9 Oct 2019 09:18:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730307AbfJIJSd (ORCPT ); Wed, 9 Oct 2019 05:18:33 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:4235 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726068AbfJIJSd (ORCPT ); Wed, 9 Oct 2019 05:18:33 -0400 X-UUID: c90e3ccb152042caa9be513527ccfcb0-20191009 X-UUID: c90e3ccb152042caa9be513527ccfcb0-20191009 Received: from mtkcas34.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 477343159; Wed, 09 Oct 2019 17:18:26 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 17:18:23 +0800 Received: from [172.21.77.4] (172.21.77.4) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 17:18:23 +0800 Message-ID: <1570612706.7713.2.camel@mtksdaap41> Subject: Re: [PATCH v5, 16/32] drm/mediatek: add component OVL_2L1 From: CK Hu To: CC: Philipp Zabel , Rob Herring , Matthias Brugger , "David Airlie" , Daniel Vetter , Mark Rutland , , , , , Date: Wed, 9 Oct 2019 17:18:26 +0800 In-Reply-To: <1567090254-15566-17-git-send-email-yongqiang.niu@mediatek.com> References: <1567090254-15566-1-git-send-email-yongqiang.niu@mediatek.com> <1567090254-15566-17-git-send-email-yongqiang.niu@mediatek.com> Content-Type: text/plain; charset="UTF-8" X-Mailer: Evolution 3.10.4-0ubuntu2 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-TM-SNTS-SMTP: 366CB8B7A69E315B8B0799225F3142C166BA891FDF40BC99C87ADF8E19ED78182000:8 X-MTK: N Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, Yongqiang: On Thu, 2019-08-29 at 22:50 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu > > This patch add component OVL_2L1 > Applied to mediatek-drm-next-5.5 [1], thanks. [1] https://github.com/ckhu-mediatek/linux.git-tags/commits/mediatek-drm-next-5.5 Regards, CK > Signed-off-by: Yongqiang Niu > Reviewed-by: CK Hu > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 1 + > drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > index 4200f89..af8e872 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c > @@ -260,6 +260,7 @@ struct mtk_ddp_comp_match { > [DDP_COMPONENT_OVL0] = { MTK_DISP_OVL, 0, NULL }, > [DDP_COMPONENT_OVL1] = { MTK_DISP_OVL, 1, NULL }, > [DDP_COMPONENT_OVL_2L0] = { MTK_DISP_OVL_2L, 0, NULL }, > + [DDP_COMPONENT_OVL_2L1] = { MTK_DISP_OVL_2L, 1, NULL }, > [DDP_COMPONENT_PWM0] = { MTK_DISP_PWM, 0, NULL }, > [DDP_COMPONENT_PWM1] = { MTK_DISP_PWM, 1, NULL }, > [DDP_COMPONENT_PWM2] = { MTK_DISP_PWM, 2, NULL }, > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > index 9caec2d..962d14a 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h > @@ -52,6 +52,7 @@ enum mtk_ddp_comp_id { > DDP_COMPONENT_OD1, > DDP_COMPONENT_OVL0, > DDP_COMPONENT_OVL_2L0, > + DDP_COMPONENT_OVL_2L1, > DDP_COMPONENT_OVL1, > DDP_COMPONENT_PWM0, > DDP_COMPONENT_PWM1,