Re: [PATCH 7/7] clk: zynqmp: Fix fractional clock check

Michael Tretter
2019-11-21T14:41:58Z

On Tue, 12 Nov 2019 05:16:20 -0800, Rajan Vaja wrote:
> Firmware driver sets BIT(4) to BIT(7) as custom type flags. To make
> divider as fractional divider firmware sets BIT(4). So add support
> for custom type flag and use BIT(4) of custom type flag as CLOCK_FRAC
> bit.
>
> Add a new field to the clock_topology to store custom type flags.
>
> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com>
> ---
> drivers/clk/zynqmp/clk-zynqmp.h | 1 +
> drivers/clk/zynqmp/clkc.c | 4 ++++
> drivers/clk/zynqmp/divider.c | 7 +++----
> 3 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/clk/zynqmp/clk-zynqmp.h b/drivers/clk/zynqmp/clk-zynqmp.h
> index fec9a15..5beeb41 100644
> --- a/drivers/clk/zynqmp/clk-zynqmp.h
> +++ b/drivers/clk/zynqmp/clk-zynqmp.h
> @@ -30,6 +30,7 @@ struct clock_topology {
> u32 type;
> u32 flag;
> u32 type_flag;
> + u8 custom_type_flag;
> };
>
> struct clk_hw *zynqmp_clk_register_pll(const char *name, u32 clk_id,
> diff --git a/drivers/clk/zynqmp/clkc.c b/drivers/clk/zynqmp/clkc.c
> index 10e89f2..4dd8413 100644
> --- a/drivers/clk/zynqmp/clkc.c
> +++ b/drivers/clk/zynqmp/clkc.c
> @@ -84,6 +84,7 @@ struct name_resp {
>
> struct topology_resp {
> #define CLK_TOPOLOGY_TYPE GENMASK(3, 0)
> +#define CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS GENMASK(7, 4)
> #define CLK_TOPOLOGY_FLAGS GENMASK(23, 8)
> #define CLK_TOPOLOGY_TYPE_FLAGS GENMASK(31, 24)
> u32 topology[CLK_GET_TOPOLOGY_RESP_WORDS];
> @@ -396,6 +397,9 @@ static int __zynqmp_clock_get_topology(struct clock_topology *topology,
> topology[*nnodes].type_flag =
> FIELD_GET(CLK_TOPOLOGY_TYPE_FLAGS,
> response->topology[i]);
> + topology[*nnodes].custom_type_flag =
> + FIELD_GET(CLK_TOPOLOGY_CUSTOM_TYPE_FLAGS,
> + response->topology[i]);
> (*nnodes)++;
> }
>
> diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c
> index 67aa88c..e700504 100644
> --- a/drivers/clk/zynqmp/divider.c
> +++ b/drivers/clk/zynqmp/divider.c
> @@ -25,7 +25,7 @@
> #define to_zynqmp_clk_divider(_hw) \
> container_of(_hw, struct zynqmp_clk_divider, hw)
>
> -#define CLK_FRAC BIT(13) /* has a fractional parent */
> +#define CLK_FRAC BIT(4) /* has a fractional parent */

Still NACK. This breaks the compatibility with the mainline TF-A. The
bit is now a different from the bit than in the previous version of
that patch. Moving the flag to custom_type_flags is fine, but please
make sure that you stay backwards compatible to existing versions of the
TF-A.

Michael

>
> /**
> * struct zynqmp_clk_divider - adjustable divider clock
> @@ -279,13 +279,12 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name,
>
> init.name = name;
> init.ops = &zynqmp_clk_divider_ops;
> - /* CLK_FRAC is not defined in the common clk framework */
> - init.flags = nodes->flag & ~CLK_FRAC;
> + init.flags = nodes->flag;
> init.parent_names = parents;
> init.num_parents = 1;
>
> /* struct clk_divider assignments */
> - div->is_frac = !!(nodes->flag & CLK_FRAC);
> + div->is_frac = !!(nodes->custom_type_flag & CLK_FRAC);
> div->flags = nodes->type_flag;
> div->hw.init = &init;
> div->clk_id = clk_id;