Re: [PATCH v4 7/7] drm/mediatek: apply CMDQ control flow

CK Hu
2019-12-06T02:55:09Z

Hi, Bibby:

On Thu, 2019-12-05 at 17:27 +0800, Bibby Hsieh wrote:
> Unlike other SoCs, MT8183 does not have "shadow"
> registers for performaing an atomic video mode
> set or page flip at vblank/vsync.
>
> The CMDQ (Commend Queue) in MT8183 is used to help
> update all relevant display controller registers
> with critical time limation.

Reviewed-by: CK Hu <ck.hu@mediatek.com>
>
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
> Signed-off-by: CK Hu <ck.hu@mediatek.com>
> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Bibby Hsieh <bibby.hsieh@mediatek.com>
> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
> ---
> drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 56 +++++++++++++++++++++----
> 1 file changed, 49 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> index 8c6231ed6f55..496dffe962af 100644
> --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c
> @@ -12,6 +12,8 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_vblank.h>
> +#include <linux/of_address.h>
> +#include <linux/soc/mediatek/mtk-cmdq.h>
>
> #include "mtk_drm_drv.h"
> #include "mtk_drm_crtc.h"
> @@ -43,6 +45,9 @@ struct mtk_drm_crtc {
> bool pending_planes;
> bool pending_async_planes;
>
> + struct cmdq_client *cmdq_client;
> + u32 cmdq_event;
> +
> void __iomem *config_regs;
> const struct mtk_mmsys_reg_data *mmsys_reg_data;
> struct mtk_disp_mutex *mutex;
> @@ -234,6 +239,13 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc,
> return NULL;
> }
>
> +#ifdef CONFIG_MTK_CMDQ
> +static void ddp_cmdq_cb(struct cmdq_cb_data data)
> +{
> + cmdq_pkt_destroy(data.data);
> +}
> +#endif
> +
> static int mtk_crtc_ddp_hw_init(struct mtk_drm_crtc *mtk_crtc)
> {
> struct drm_crtc *crtc = &mtk_crtc->base;
> @@ -378,7 +390,8 @@ static void mtk_crtc_ddp_hw_fini(struct mtk_drm_crtc *mtk_crtc)
> }
> }
>
> -static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> +static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
> + struct cmdq_pkt *cmdq_handle)
> {
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
> @@ -394,7 +407,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
> if (state->pending_config) {
> mtk_ddp_comp_config(comp, state->pending_width,
> state->pending_height,
> - state->pending_vrefresh, 0, NULL);
> + state->pending_vrefresh, 0,
> + cmdq_handle);
>
> state->pending_config = false;
> }
> @@ -414,7 +428,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
>
> if (comp)
> mtk_ddp_comp_layer_config(comp, local_layer,
> - plane_state, NULL);
> + plane_state,
> + cmdq_handle);
> plane_state->pending.config = false;
> }
> mtk_crtc->pending_planes = false;
> @@ -435,7 +450,8 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
>
> if (comp)
> mtk_ddp_comp_layer_config(comp, local_layer,
> - plane_state, NULL);
> + plane_state,
> + cmdq_handle);
> plane_state->pending.async_config = false;
> }
> mtk_crtc->pending_async_planes = false;
> @@ -444,6 +460,7 @@ static void mtk_crtc_ddp_config(struct drm_crtc *crtc)
>
> static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
> {
> + struct cmdq_pkt *cmdq_handle;
> struct drm_crtc *crtc = &mtk_crtc->base;
> struct mtk_drm_private *priv = crtc->dev->dev_private;
> unsigned int pending_planes = 0, pending_async_planes = 0;
> @@ -472,9 +489,18 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc)
>
> if (priv->data->shadow_register) {
> mtk_disp_mutex_acquire(mtk_crtc->mutex);
> - mtk_crtc_ddp_config(crtc);
> + mtk_crtc_ddp_config(crtc, NULL);
> mtk_disp_mutex_release(mtk_crtc->mutex);
> }
> +#ifdef CONFIG_MTK_CMDQ
> + if (mtk_crtc->cmdq_client) {
> + cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE);
> + cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
> + cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event);
> + mtk_crtc_ddp_config(crtc, cmdq_handle);
> + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle);
> + }
> +#endif
> mutex_unlock(&mtk_crtc->hw_lock);
> }
>
> @@ -643,8 +669,8 @@ void mtk_crtc_ddp_irq(struct drm_crtc *crtc, struct mtk_ddp_comp *comp)
> struct mtk_drm_crtc *mtk_crtc = to_mtk_crtc(crtc);
> struct mtk_drm_private *priv = crtc->dev->dev_private;
>
> - if (!priv->data->shadow_register)
> - mtk_crtc_ddp_config(crtc);
> + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client)
> + mtk_crtc_ddp_config(crtc, NULL);
>
> mtk_drm_finish_page_flip(mtk_crtc);
> }
> @@ -787,5 +813,21 @@ int mtk_drm_crtc_create(struct drm_device *drm_dev,
> priv->num_pipes++;
> mutex_init(&mtk_crtc->hw_lock);
>
> +#ifdef CONFIG_MTK_CMDQ
> + mtk_crtc->cmdq_client =
> + cmdq_mbox_create(dev, drm_crtc_index(&mtk_crtc->base),
> + 2000);
> + if (IS_ERR(mtk_crtc->cmdq_client)) {
> + dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
> + drm_crtc_index(&mtk_crtc->base));
> + mtk_crtc->cmdq_client = NULL;
> + }
> + ret = of_property_read_u32_index(dev->of_node, "mediatek,gce-events",
> + drm_crtc_index(&mtk_crtc->base),
> + &mtk_crtc->cmdq_event);
> + if (ret)
> + dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
> + drm_crtc_index(&mtk_crtc->base));
> +#endif
> return 0;
> }