[PATCH 09/21] perf/x86: Expose CPUID enumeration bits for arch LBR

kan.liang
2020-06-19T14:08:09Z

The LBR capabilities of Architecture LBR are retrieved from the CPUID
enumeration once at boot time. The capabilities have to be saved for
future usage.

Several new fields in x86_pmu are added to indicate the capabilities.
The fields will be used in the following patches.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/perf_event.h | 44 ++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 44 insertions(+)

diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index e33d348..cbfc55b 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -689,6 +689,50 @@ struct x86_pmu {
const int *lbr_sel_map; /* lbr_select mappings */
bool lbr_double_abort; /* duplicated lbr aborts */
bool lbr_pt_coexist; /* (LBR|BTS) may coexist with PT */
+ bool arch_lbr; /* Arch LBR supported */
+
+ /* Arch LBR Capabilities */
+ union {
+ struct {
+ /* Supported LBR depth values */
+ unsigned int arch_lbr_depth_mask:8;
+
+ unsigned int reserved:22;
+
+ /* Deep C-state Reset */
+ unsigned int arch_lbr_deep_c_reset:1;
+
+ /* IP values contain LIP */
+ unsigned int arch_lbr_lip:1;
+ };
+ unsigned int arch_lbr_eax;
+ };
+ union {
+ struct {
+ /* CPL Filtering Supported */
+ unsigned int arch_lbr_cpl:1;
+
+ /* Branch Filtering Supported */
+ unsigned int arch_lbr_filter:1;
+
+ /* Call-stack Mode Supported */
+ unsigned int arch_lbr_call_stack:1;
+ };
+ unsigned int arch_lbr_ebx;
+ };
+ union {
+ struct {
+ /* Mispredict Bit Supported */
+ unsigned int arch_lbr_mispred:1;
+
+ /* Timed LBRs Supported */
+ unsigned int arch_lbr_timed_lbr:1;
+
+ /* Branch Type Field Supported */
+ unsigned int arch_lbr_br_type:1;
+ };
+ unsigned int arch_lbr_ecx;
+ };

void (*lbr_enable)(bool pmi);
void (*lbr_disable)(void);
--
2.7.4