[PATCH 03/21] perf/x86/intel/lbr: Add pointer for LBR reset

kan.liang
2020-06-19T14:07:54Z

The method to reset Architectural LBRs is different from previous
model-specific LBR. Perf has to implement a different function.

A function pointer is introduced for LBR reset. The enum of
LBR_FORMAT_* is also moved to perf_event.h. Perf should initialize the
corresponding functions at boot time, and avoid checking lbr_format at
run time.

The current 64-bit LBR reset function is set as default.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 5 +++++
arch/x86/events/intel/lbr.c | 20 +++-----------------
arch/x86/events/perf_event.h | 16 ++++++++++++++++
3 files changed, 24 insertions(+), 17 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 56966fc..995acdb 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3954,6 +3954,7 @@ static __initconst const struct x86_pmu core_pmu = {

.lbr_enable = intel_pmu_lbr_enable,
.lbr_disable = intel_pmu_lbr_disable,
+ .lbr_reset = intel_pmu_lbr_reset_64,
};

static __initconst const struct x86_pmu intel_pmu = {
@@ -4002,6 +4003,7 @@ static __initconst const struct x86_pmu intel_pmu = {

.lbr_enable = intel_pmu_lbr_enable,
.lbr_disable = intel_pmu_lbr_disable,
+ .lbr_reset = intel_pmu_lbr_reset_64,
};

static __init void intel_clovertown_quirk(void)
@@ -4628,6 +4630,9 @@ __init int intel_pmu_init(void)
x86_pmu.intel_cap.capabilities = capabilities;
}

+ if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
+ x86_pmu.lbr_reset = intel_pmu_lbr_reset_32;
+
intel_ds_init();

x86_add_quirk(intel_arch_events_quirk); /* Install first, so it runs last */
diff --git a/arch/x86/events/intel/lbr.c b/arch/x86/events/intel/lbr.c
index bdd38b6..ff320d1 100644
--- a/arch/x86/events/intel/lbr.c
+++ b/arch/x86/events/intel/lbr.c
@@ -8,17 +8,6 @@

#include "../perf_event.h"

-enum {
- LBR_FORMAT_32 = 0x00,
- LBR_FORMAT_LIP = 0x01,
- LBR_FORMAT_EIP = 0x02,
- LBR_FORMAT_EIP_FLAGS = 0x03,
- LBR_FORMAT_EIP_FLAGS2 = 0x04,
- LBR_FORMAT_INFO = 0x05,
- LBR_FORMAT_TIME = 0x06,
- LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
-};
-
static const enum {
LBR_EIP_FLAGS = 1,
LBR_TSX = 2,
@@ -194,7 +183,7 @@ void intel_pmu_lbr_disable(void)
wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctl);
}

-static void intel_pmu_lbr_reset_32(void)
+void intel_pmu_lbr_reset_32(void)
{
int i;

@@ -202,7 +191,7 @@ static void intel_pmu_lbr_reset_32(void)
wrmsrl(x86_pmu.lbr_from + i, 0);
}

-static void intel_pmu_lbr_reset_64(void)
+void intel_pmu_lbr_reset_64(void)
{
int i;

@@ -221,10 +210,7 @@ void intel_pmu_lbr_reset(void)
if (!x86_pmu.lbr_nr)
return;

- if (x86_pmu.intel_cap.lbr_format == LBR_FORMAT_32)
- intel_pmu_lbr_reset_32();
- else
- intel_pmu_lbr_reset_64();
+ x86_pmu.lbr_reset();

cpuc->last_task_ctx = NULL;
cpuc->last_log_id = 0;
diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h
index a61a076..abf95ef 100644
--- a/arch/x86/events/perf_event.h
+++ b/arch/x86/events/perf_event.h
@@ -179,6 +179,17 @@ struct x86_perf_task_context;
#define MAX_LBR_ENTRIES 32

enum {
+ LBR_FORMAT_32 = 0x00,
+ LBR_FORMAT_LIP = 0x01,
+ LBR_FORMAT_EIP = 0x02,
+ LBR_FORMAT_EIP_FLAGS = 0x03,
+ LBR_FORMAT_EIP_FLAGS2 = 0x04,
+ LBR_FORMAT_INFO = 0x05,
+ LBR_FORMAT_TIME = 0x06,
+ LBR_FORMAT_MAX_KNOWN = LBR_FORMAT_TIME,
+};
+
+enum {
X86_PERF_KFREE_SHARED = 0,
X86_PERF_KFREE_EXCL = 1,
X86_PERF_KFREE_MAX
@@ -681,6 +692,7 @@ struct x86_pmu {

void (*lbr_enable)(bool pmi);
void (*lbr_disable)(void);
+ void (*lbr_reset)(void);

/*
* Intel PT/LBR/BTS are exclusive
@@ -1056,6 +1068,10 @@ u64 lbr_from_signext_quirk_wr(u64 val);

void intel_pmu_lbr_reset(void);

+void intel_pmu_lbr_reset_32(void);
+
+void intel_pmu_lbr_reset_64(void);
+
void intel_pmu_lbr_add(struct perf_event *event);

void intel_pmu_lbr_del(struct perf_event *event);
--
2.7.4