Re: [PATCH 20/21] perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch

Liang, Kan
2020-06-19T22:28:23Z

On 6/19/2020 3:41 PM, Peter Zijlstra wrote:
> On Fri, Jun 19, 2020 at 07:04:08AM -0700, kan.liang@linux.intel.com wrote:
>> The XSAVE instruction requires 64-byte alignment for state buffers. A
>> 64-byte aligned kmem_cache is created for architecture LBR.
>
>> + pmu->task_ctx_cache = create_lbr_kmem_cache(size,
>> + XSAVE_ALIGNMENT);
>
>> +struct x86_perf_task_context_arch_lbr_xsave {
>> + struct x86_perf_task_context_opt opt;
>> + union {
>> + struct xregs_state xsave;
>
> Due to x86_perf_task_context_opt, what guarantees you're actually at the
> required alignment here?

Now it relies on the compiler. The struct xregs_state has 'aligned(64)'
attribute applied.
I think we probably need a padding to get rid of the dependency for the
compiler.

+ union {
+ struct x86_perf_task_context_opt opt;
+ u8 padding[64];
+ };

Thanks,
Kan

>
>> + struct {
>> + struct fxregs_state i387;
>> + struct xstate_header header;
>> + struct arch_lbr_state lbr;
>> + };
>> + };
>> +};