From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 140BAC433E0 for ; Tue, 30 Jun 2020 21:01:27 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id E12E52074D for ; Tue, 30 Jun 2020 21:01:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727809AbgF3VBH (ORCPT ); Tue, 30 Jun 2020 17:01:07 -0400 Received: from mga09.intel.com ([134.134.136.24]:26203 "EHLO mga09.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726947AbgF3VBG (ORCPT ); Tue, 30 Jun 2020 17:01:06 -0400 IronPort-SDR: dxIgbb5/46utS22REAwuKsEyzG7tC3hgYt/AFi0SjZM0QUteiBoX0HAFFG8dm6ufWLHmiTzbuo YTfS+EGgxwFA== X-IronPort-AV: E=McAfee;i="6000,8403,9668"; a="147935008" X-IronPort-AV: E=Sophos;i="5.75,298,1589266800"; d="scan'208";a="147935008" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Jun 2020 14:01:05 -0700 IronPort-SDR: SpsS6sneonBqQA49OBcqy5Nc5QY/QZttXq0eNjX+YI036tiPW58nCvbYd7VLT5bmD/IYJfHeFv jofzunfQYXUQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,298,1589266800"; d="scan'208";a="425337228" Received: from jacob-builder.jf.intel.com ([10.7.199.155]) by orsmga004.jf.intel.com with ESMTP; 30 Jun 2020 14:01:05 -0700 From: Jacob Pan To: iommu@lists.linux-foundation.org, LKML , "Lu Baolu" , Joerg Roedel , David Woodhouse Cc: Yi Liu , "Tian, Kevin" , Raj Ashok , Eric Auger , Jacob Pan Subject: [PATCH v2 1/7] iommu/vt-d: Enforce PASID devTLB field mask Date: Tue, 30 Jun 2020 14:07:32 -0700 Message-Id: <1593551258-39854-2-git-send-email-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1593551258-39854-1-git-send-email-jacob.jun.pan@linux.intel.com> References: <1593551258-39854-1-git-send-email-jacob.jun.pan@linux.intel.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Liu Yi L Set proper masks to avoid invalid input spillover to reserved bits. Acked-by: Lu Baolu Signed-off-by: Liu Yi L Signed-off-by: Jacob Pan --- include/linux/intel-iommu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h index 4100bd224f5c..729386ca8122 100644 --- a/include/linux/intel-iommu.h +++ b/include/linux/intel-iommu.h @@ -380,8 +380,8 @@ enum { #define QI_DEV_EIOTLB_ADDR(a) ((u64)(a) & VTD_PAGE_MASK) #define QI_DEV_EIOTLB_SIZE (((u64)1) << 11) -#define QI_DEV_EIOTLB_GLOB(g) ((u64)g) -#define QI_DEV_EIOTLB_PASID(p) (((u64)p) << 32) +#define QI_DEV_EIOTLB_GLOB(g) ((u64)(g) & 0x1) +#define QI_DEV_EIOTLB_PASID(p) ((u64)((p) & 0xfffff) << 32) #define QI_DEV_EIOTLB_SID(sid) ((u64)((sid) & 0xffff) << 16) #define QI_DEV_EIOTLB_QDEP(qd) ((u64)((qd) & 0x1f) << 4) #define QI_DEV_EIOTLB_PFSID(pfsid) (((u64)(pfsid & 0xf) << 12) | \ -- 2.7.4