From: <light.hsieh@mediatek.com>
To: <linus.walleij@linaro.org>
Cc: <linux-mediatek@lists.infradead.org>,
<linux-gpio@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<sean.wang@kernel.org>, <kuohong.wang@mediatek.com>,
Light Hsieh <light.hsieh@mediatek.com>
Subject: [PATCH v1 2/2] pinctrl: mediatek: make MediaTek MT6765 pinctrl driver support race-free register access
Date: Tue, 18 Aug 2020 16:36:16 +0800 [thread overview]
Message-ID: <1597739776-15944-2-git-send-email-light.hsieh@mediatek.com> (raw)
In-Reply-To: <1597739776-15944-1-git-send-email-light.hsieh@mediatek.com>
From: Light Hsieh <light.hsieh@mediatek.com>
This patch make MediaTek MT6765 pinctrl driver support race-free register access
Signed-off-by: Light Hsieh <light.hsieh@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mt6765.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt6765.c b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
index 2c59d39..f33c371 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt6765.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt6765.c
@@ -1071,6 +1071,8 @@
.ngrps = ARRAY_SIZE(mtk_pins_mt6765),
.eint_hw = &mt6765_eint_hw,
.gpio_m = 0,
+ .race_free_access = true,
+ .mwr_field_width = 4,
.base_names = mt6765_pinctrl_register_base_names,
.nbase_names = ARRAY_SIZE(mt6765_pinctrl_register_base_names),
.bias_set_combo = mtk_pinconf_bias_set_combo,
--
1.8.1.1.dirty
next prev parent reply other threads:[~2020-08-18 8:36 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-08-18 8:36 [PATCH v1 1/2] pinctrl: mediatek: support access registers without race-condition light.hsieh
2020-08-18 8:36 ` light.hsieh [this message]
2020-08-19 23:11 ` Sean Wang
2020-08-21 4:47 ` Light Hsieh
2020-08-21 9:59 ` Sean Wang
2020-08-21 10:44 ` Light Hsieh
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