Re: [PATCH v2 2/3] clk: rockchip: Add dt-binding header for rk3576

[Krzysztof Kozlowski <krzk@kernel.org>]

On 02/08/2024 23:35, Detlev Casanova wrote:
> From: Elaine Zhang <zhangqing@rock-chips.com>
> 
> Add the dt-bindings header for the rk3576, that gets shared between
> the clock controller and the clock references in the dts.
> 
> Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
> Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
> [rebased, separate clocks and resets]
> Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>

Please use subject prefixes matching the subsystem. You can get them for
example with `git log --oneline -- DIRECTORY_OR_FILE` on the directory
your patch is touching. For bindings, the preferred subjects are
explained here:
https://www.kernel.org/doc/html/latest/devicetree/bindings/submitting-patches.html#i-for-patch-submitters


> ---
>  .../dt-bindings/clock/rockchip,rk3576-cru.h   | 589 ++++++++++++++++++
>  .../dt-bindings/reset/rockchip,rk3576-cru.h   | 484 ++++++++++++++
>  2 files changed, 1073 insertions(+)
>  create mode 100644 include/dt-bindings/clock/rockchip,rk3576-cru.h
>  create mode 100644 include/dt-bindings/reset/rockchip,rk3576-cru.h

These are bindings. Must be squashed with previous patch.

> 
> diff --git a/include/dt-bindings/clock/rockchip,rk3576-cru.h b/include/dt-bindings/clock/rockchip,rk3576-cru.h
> new file mode 100644
> index 0000000000000..14b54543d1a11
> --- /dev/null
> +++ b/include/dt-bindings/clock/rockchip,rk3576-cru.h
> @@ -0,0 +1,589 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */

Weird license. Why not using recommended one?

> +/*
> + * Copyright (c) 2023 Rockchip Electronics Co. Ltd.
> + * Author: Elaine Zhang <zhangqing@rock-chips.com>
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
> +#define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H
> +
> +/* cru-clocks indices */
> +
> +/* cru plls */
> +#define PLL_BPLL			1
> +#define PLL_LPLL			3
> +#define PLL_VPLL			4
> +#define PLL_AUPLL			5
> +#define PLL_CPLL			6
> +#define PLL_GPLL			7
> +#define PLL_PPLL			9

Nope, indices start from 1 and are incremented continuously.



Best regards,
Krzysztof