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From: Weiyi Lu <weiyi.lu@mediatek.com>
To: Yingjoe Chen <yingjoe.chen@mediatek.com>
Cc: Matthias Brugger <matthias.bgg@gmail.com>,
	Rob Herring <robh@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
	Nicolas Boichat <drinkcat@chromium.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-mediatek@lists.infradead.org>, <linux-clk@vger.kernel.org>,
	<srv_heupstream@mediatek.com>
Subject: Re: [PATCH v5 14/24] clk: mediatek: Add MT8192 imp i2c wrapper clock support
Date: Wed, 18 Nov 2020 11:49:42 +0800	[thread overview]
Message-ID: <1605671382.23622.8.camel@mtksdaap41> (raw)
In-Reply-To: <1605667293.8636.5.camel@mtksdaap41>

On Wed, 2020-11-18 at 10:41 +0800, Yingjoe Chen wrote:
> On Mon, 2020-11-09 at 10:03 +0800, Weiyi Lu wrote:
> > Add MT8192 imp i2c wrapper clock provider
> > 
> > Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
> > ---
> >  drivers/clk/mediatek/Kconfig                   |   6 ++
> >  drivers/clk/mediatek/Makefile                  |   1 +
> >  drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c | 119 +++++++++++++++++++++++++
> >  3 files changed, 126 insertions(+)
> >  create mode 100644 drivers/clk/mediatek/clk-mt8192-imp_iic_wrap.c
> > 
> > diff --git a/drivers/clk/mediatek/Kconfig b/drivers/clk/mediatek/Kconfig
> > index eb549f8..8acc7d6 100644
> > --- a/drivers/clk/mediatek/Kconfig
> > +++ b/drivers/clk/mediatek/Kconfig
> > @@ -515,6 +515,12 @@ config COMMON_CLK_MT8192_IMGSYS
> >  	help
> >  	  This driver supports MediaTek MT8192 imgsys and imgsys2 clocks.
> >  
> > +config COMMON_CLK_MT8192_IMP_IIC_WRAP
> > +	bool "Clock driver for MediaTek MT8192 imp_iic_wrap"
> > +	depends on COMMON_CLK_MT8192
> > +	help
> > +	  This driver supports MediaTek MT8192 imp_iic_wrap clocks.
> > +
> >  config COMMON_CLK_MT8516
> >  	bool "Clock driver for MediaTek MT8516"
> >  	depends on ARCH_MEDIATEK || COMPILE_TEST
> 
> <...>
> 
> > +
> > +static struct platform_driver clk_mt8192_imp_iic_wrap_drv = {
> > +	.probe = mtk_clk_simple_probe,
> 
> Good to have this generic probe function. Now several mtk clk drivers
> are just a few data.
> 
> But this series still add >10 configs for mt8192 clock drivers. Why do
> we need separate configs for clocks of different domain? I don't think
> they need lots of resource. We should review the rationale and reduce
> the numbers. 
> 
Hi Joe,

Thanks for reviewing.

There have been some discussions in patch[1] as to why the subsystem
clocks are now separated by different configs.
And we do need these clocks to be optional on some MediatTek SoC
platform.

I thought it it now a rationale number of subsystem clock provider
drivers. In this series, we have reduced from 23 to 12.

[1]
https://patchwork.kernel.org/project/linux-mediatek/patch/1460621514-65191-5-git-send-email-jamesjj.liao@mediatek.com/


> 
> Joe.C
> 
> 


  reply	other threads:[~2020-11-18  3:50 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-11-09  2:03 [PATCH v5 00/24] Mediatek MT8192 clock support Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 01/24] dt-bindings: ARM: Mediatek: Add new document bindings of imp i2c wrapper controller Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 02/24] dt-bindings: ARM: Mediatek: Add new document bindings of mdpsys controller Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 03/24] dt-bindings: ARM: Mediatek: Add new document bindings of msdc controller Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 04/24] dt-bindings: ARM: Mediatek: Add new document bindings of scp adsp controller Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 05/24] dt-bindings: ARM: Mediatek: Document bindings of MT8192 clock controllers Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 06/24] clk: mediatek: Add dt-bindings of MT8192 clocks Weiyi Lu
2020-11-10 16:03   ` Rob Herring
2020-11-09  2:03 ` [PATCH v5 07/24] clk: mediatek: Fix asymmetrical PLL enable and disable control Weiyi Lu
2020-11-18  3:55   ` Ikjoon Jang
2020-11-18  5:21     ` Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 08/24] clk: mediatek: Add configurable enable control to mtk_pll_data Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 09/24] clk: mediatek: Add mtk_clk_simple_probe() to simplify clock providers Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 10/24] clk: mediatek: Add MT8192 basic clocks support Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 11/24] clk: mediatek: Add MT8192 audio clock support Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 12/24] clk: mediatek: Add MT8192 camsys " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 13/24] clk: mediatek: Add MT8192 imgsys " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 14/24] clk: mediatek: Add MT8192 imp i2c wrapper " Weiyi Lu
2020-11-18  2:41   ` Yingjoe Chen
2020-11-18  3:49     ` Weiyi Lu [this message]
2020-11-09  2:03 ` [PATCH v5 15/24] clk: mediatek: Add MT8192 ipesys " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 16/24] clk: mediatek: Add MT8192 mdpsys " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 17/24] clk: mediatek: Add MT8192 mfgcfg " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 18/24] clk: mediatek: Add MT8192 mmsys " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 19/24] clk: mediatek: Add MT8192 msdc " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 20/24] clk: mediatek: Add MT8192 scp adsp " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 21/24] clk: mediatek: Add MT8192 vdecsys " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 22/24] clk: mediatek: Add MT8192 vencsys " Weiyi Lu
2020-11-09  2:03 ` [PATCH v5 23/24] arm64: dts: mediatek: Add mt8192 clock controllers Weiyi Lu
2020-11-23  4:02   ` Ikjoon Jang
2020-12-17  8:53     ` Stephen Boyd
2020-11-09  2:03 ` [PATCH v5 24/24] arm64: dts: mediatek: Correct UART0 bus clock of MT8192 Weiyi Lu
2020-12-17  9:19 ` [PATCH v5 00/24] Mediatek MT8192 clock support Stephen Boyd

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