From: kan.liang@linux.intel.com
To: peterz@infradead.org, acme@kernel.org, mingo@kernel.org,
linux-kernel@vger.kernel.org
Cc: eranian@google.com, namhyung@kernel.org, jolsa@redhat.com,
ak@linux.intel.com, yao.jin@linux.intel.com, mpe@ellerman.id.au,
maddy@linux.vnet.ibm.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V2 3/5] perf/x86/intel: Filter unsupported Topdown metrics event
Date: Wed, 27 Jan 2021 07:38:43 -0800 [thread overview]
Message-ID: <1611761925-159055-4-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1611761925-159055-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
Current perf doesn't check the index of a Topdown metrics event before
updating the event. A perf tool user may get a value from an unsupported
Topdown metrics event.
For example, the L2 topdown event, cpu/event=0x00,umask=0x84/, is not
supported on Ice Lake. A perf tool user may mistakenly use the
unsupported events via RAW format. In this case, the scheduler follows
the unknown event handling and assigns a GP counter to the event. The
icl_get_topdown_value() returns the value of the slots to the event.
The perf tool user will get the value for the unsupported
Topdown metrics event.
Add a check in the __icl_update_topdown_event() and avoid updating
unsupported events.
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/intel/core.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 8eba41b..b02d482 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -2319,6 +2319,17 @@ static void __icl_update_topdown_event(struct perf_event *event,
{
u64 delta, last = 0;
+ /*
+ * Although the unsupported topdown events are not exposed to users,
+ * users may mistakenly use the unsupported events via RAW format.
+ * For example, using L2 topdown event, cpu/event=0x00,umask=0x84/,
+ * on Ice Lake. In this case, the scheduler follows the unknown
+ * event handling and assigns a GP counter to the event.
+ * Check the case, and avoid updating unsupported events.
+ */
+ if (event->hw.idx < INTEL_PMC_IDX_FIXED)
+ return;
+
delta = icl_get_topdown_value(event, slots, metrics);
if (last_slots)
last = icl_get_topdown_value(event, last_slots, last_metrics);
--
2.7.4
next prev parent reply other threads:[~2021-01-27 15:48 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-27 15:38 [PATCH V2 0/5] perf core PMU support for Sapphire Rapids (Kernel) kan.liang
2021-01-27 15:38 ` [PATCH V2 1/5] perf/core: Add PERF_SAMPLE_WEIGHT_STRUCT kan.liang
2021-01-27 19:03 ` Peter Zijlstra
2021-01-27 21:54 ` Liang, Kan
2021-01-27 15:38 ` [PATCH V2 2/5] perf/x86/intel: Factor out intel_update_topdown_event() kan.liang
2021-01-27 15:38 ` kan.liang [this message]
2021-01-27 19:13 ` [PATCH V2 3/5] perf/x86/intel: Filter unsupported Topdown metrics event Peter Zijlstra
2021-01-27 20:50 ` Liang, Kan
2021-01-27 15:38 ` [PATCH V2 4/5] perf/x86/intel: Add perf core PMU support for Sapphire Rapids kan.liang
2021-01-27 15:38 ` [PATCH V2 5/5] perf/x86/intel: Support CPUID 10.ECX to disable fixed counters kan.liang
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