* [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
@ 2021-01-30 20:07 Md Sadre Alam
2021-02-05 17:56 ` mdalam
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Md Sadre Alam @ 2021-01-30 20:07 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, boris.brezillon,
manivannan.sadhasivam, linux-mtd, linux-kernel
Cc: mdalam, sricharan
This change will remove unused register name macro NAND_DEV1_ECC_CFG.
Since this register was only available in QPIC version 1.4.20 ipq40xx
and it was not used. In QPIC version 1.5 on wards this register got
removed.In QPIC version 2.0 0x2c offset is updated with register
NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
with offset 0x2c.
Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
---
drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
index 9484be8..c238a35 100644
--- a/drivers/mtd/nand/raw/qcom_nandc.c
+++ b/drivers/mtd/nand/raw/qcom_nandc.c
@@ -27,7 +27,7 @@
#define NAND_DEV0_CFG0 0x20
#define NAND_DEV0_CFG1 0x24
#define NAND_DEV0_ECC_CFG 0x28
-#define NAND_DEV1_ECC_CFG 0x2c
+#define NAND_AUTO_STATUS_EN 0x2c
#define NAND_DEV1_CFG0 0x30
#define NAND_DEV1_CFG1 0x34
#define NAND_READ_ID 0x40
--
2.7.4
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
2021-01-30 20:07 [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset Md Sadre Alam
@ 2021-02-05 17:56 ` mdalam
2021-02-05 18:01 ` Miquel Raynal
2021-02-10 8:58 ` Manivannan Sadhasivam
2021-03-02 16:33 ` Miquel Raynal
2 siblings, 1 reply; 5+ messages in thread
From: mdalam @ 2021-02-05 17:56 UTC (permalink / raw)
To: miquel.raynal, richard, vigneshr, boris.brezillon,
manivannan.sadhasivam, linux-mtd, linux-kernel
Cc: sricharan
On 2021-01-31 01:37, Md Sadre Alam wrote:
> This change will remove unused register name macro NAND_DEV1_ECC_CFG.
> Since this register was only available in QPIC version 1.4.20 ipq40xx
> and it was not used. In QPIC version 1.5 on wards this register got
> removed.In QPIC version 2.0 0x2c offset is updated with register
> NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
> with offset 0x2c.
>
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Ping! Is any additional info needed for this patch ?
> ---
> drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c
> b/drivers/mtd/nand/raw/qcom_nandc.c
> index 9484be8..c238a35 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -27,7 +27,7 @@
> #define NAND_DEV0_CFG0 0x20
> #define NAND_DEV0_CFG1 0x24
> #define NAND_DEV0_ECC_CFG 0x28
> -#define NAND_DEV1_ECC_CFG 0x2c
> +#define NAND_AUTO_STATUS_EN 0x2c
> #define NAND_DEV1_CFG0 0x30
> #define NAND_DEV1_CFG1 0x34
> #define NAND_READ_ID 0x40
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
2021-02-05 17:56 ` mdalam
@ 2021-02-05 18:01 ` Miquel Raynal
0 siblings, 0 replies; 5+ messages in thread
From: Miquel Raynal @ 2021-02-05 18:01 UTC (permalink / raw)
To: mdalam
Cc: richard, vigneshr, boris.brezillon, manivannan.sadhasivam,
linux-mtd, linux-kernel, sricharan
Hello,
mdalam@codeaurora.org wrote on Fri, 05 Feb 2021 23:26:33 +0530:
> On 2021-01-31 01:37, Md Sadre Alam wrote:
> > This change will remove unused register name macro NAND_DEV1_ECC_CFG.
> > Since this register was only available in QPIC version 1.4.20 ipq40xx
> > and it was not used. In QPIC version 1.5 on wards this register got
> > removed.In QPIC version 2.0 0x2c offset is updated with register
> > NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
> > with offset 0x2c.
> >
> > Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
>
> Ping! Is any additional info needed for this patch ?
The patch is fine but we are at -rc6, the NAND PR has already been
sent, I don't plan to add more patches for this release. I will apply
new patches at v5.12-rc1.
Thanks,
Miquèl
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
2021-01-30 20:07 [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset Md Sadre Alam
2021-02-05 17:56 ` mdalam
@ 2021-02-10 8:58 ` Manivannan Sadhasivam
2021-03-02 16:33 ` Miquel Raynal
2 siblings, 0 replies; 5+ messages in thread
From: Manivannan Sadhasivam @ 2021-02-10 8:58 UTC (permalink / raw)
To: Md Sadre Alam
Cc: miquel.raynal, richard, vigneshr, boris.brezillon, linux-mtd,
linux-kernel, sricharan
On Sun, Jan 31, 2021 at 01:37:16AM +0530, Md Sadre Alam wrote:
> This change will remove unused register name macro NAND_DEV1_ECC_CFG.
> Since this register was only available in QPIC version 1.4.20 ipq40xx
> and it was not used. In QPIC version 1.5 on wards this register got
> removed.In QPIC version 2.0 0x2c offset is updated with register
> NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
> with offset 0x2c.
>
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> drivers/mtd/nand/raw/qcom_nandc.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index 9484be8..c238a35 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -27,7 +27,7 @@
> #define NAND_DEV0_CFG0 0x20
> #define NAND_DEV0_CFG1 0x24
> #define NAND_DEV0_ECC_CFG 0x28
> -#define NAND_DEV1_ECC_CFG 0x2c
> +#define NAND_AUTO_STATUS_EN 0x2c
> #define NAND_DEV1_CFG0 0x30
> #define NAND_DEV1_CFG1 0x34
> #define NAND_READ_ID 0x40
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset
2021-01-30 20:07 [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset Md Sadre Alam
2021-02-05 17:56 ` mdalam
2021-02-10 8:58 ` Manivannan Sadhasivam
@ 2021-03-02 16:33 ` Miquel Raynal
2 siblings, 0 replies; 5+ messages in thread
From: Miquel Raynal @ 2021-03-02 16:33 UTC (permalink / raw)
To: Md Sadre Alam, miquel.raynal, richard, vigneshr, boris.brezillon,
manivannan.sadhasivam, linux-mtd, linux-kernel
Cc: sricharan
On Sat, 2021-01-30 at 20:07:16 UTC, Md Sadre Alam wrote:
> This change will remove unused register name macro NAND_DEV1_ECC_CFG.
> Since this register was only available in QPIC version 1.4.20 ipq40xx
> and it was not used. In QPIC version 1.5 on wards this register got
> removed.In QPIC version 2.0 0x2c offset is updated with register
> NAND_AUTO_STATUS_EN So adding this register macro NAND_AUTO_STATUS_EN
> with offset 0x2c.
>
> Signed-off-by: Md Sadre Alam <mdalam@codeaurora.org>
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.
Miquel
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-01-30 20:07 [PATCH] mtd: rawnand: qcom: Update register macro name for 0x2c offset Md Sadre Alam
2021-02-05 17:56 ` mdalam
2021-02-05 18:01 ` Miquel Raynal
2021-02-10 8:58 ` Manivannan Sadhasivam
2021-03-02 16:33 ` Miquel Raynal
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