From: kan.liang@linux.intel.com
To: peterz@infradead.org, mingo@kernel.org, linux-kernel@vger.kernel.org
Cc: acme@kernel.org, tglx@linutronix.de, bp@alien8.de,
namhyung@kernel.org, jolsa@redhat.com, ak@linux.intel.com,
yao.jin@linux.intel.com, alexander.shishkin@linux.intel.com,
adrian.hunter@intel.com, Kan Liang <kan.liang@linux.intel.com>
Subject: [PATCH V3 23/25] perf/x86/msr: Add Alder Lake CPU support
Date: Fri, 26 Mar 2021 12:02:10 -0700 [thread overview]
Message-ID: <1616785332-165261-24-git-send-email-kan.liang@linux.intel.com> (raw)
In-Reply-To: <1616785332-165261-1-git-send-email-kan.liang@linux.intel.com>
From: Kan Liang <kan.liang@linux.intel.com>
PPERF and SMI_COUNT MSRs are also supported on Alder Lake.
The External Design Specification (EDS) is not published yet. It comes
from an authoritative internal source.
The patch has been tested on real hardware.
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
---
arch/x86/events/msr.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/events/msr.c b/arch/x86/events/msr.c
index 680404c..c853b28 100644
--- a/arch/x86/events/msr.c
+++ b/arch/x86/events/msr.c
@@ -100,6 +100,8 @@ static bool test_intel(int idx, void *data)
case INTEL_FAM6_TIGERLAKE_L:
case INTEL_FAM6_TIGERLAKE:
case INTEL_FAM6_ROCKETLAKE:
+ case INTEL_FAM6_ALDERLAKE:
+ case INTEL_FAM6_ALDERLAKE_L:
if (idx == PERF_MSR_SMI || idx == PERF_MSR_PPERF)
return true;
break;
--
2.7.4
next prev parent reply other threads:[~2021-03-26 19:09 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-03-26 19:01 [PATCH V3 00/25] Add Alder Lake support for perf (kernel) kan.liang
2021-03-26 19:01 ` [PATCH V3 01/25] x86/cpufeatures: Enumerate Intel Hybrid Technology feature bit kan.liang
2021-03-26 19:01 ` [PATCH V3 02/25] x86/cpu: Add helper function to get the type of the current hybrid CPU kan.liang
2021-03-26 19:01 ` [PATCH V3 03/25] perf/x86: Track pmu in per-CPU cpu_hw_events kan.liang
2021-03-26 19:01 ` [PATCH V3 04/25] perf/x86/intel: Hybrid PMU support for perf capabilities kan.liang
2021-03-26 19:01 ` [PATCH V3 05/25] perf/x86: Hybrid PMU support for intel_ctrl kan.liang
2021-03-26 19:01 ` [PATCH V3 06/25] perf/x86: Hybrid PMU support for counters kan.liang
2021-03-26 19:01 ` [PATCH V3 07/25] perf/x86: Hybrid PMU support for unconstrained kan.liang
2021-03-26 19:01 ` [PATCH V3 08/25] perf/x86: Hybrid PMU support for hardware cache event kan.liang
2021-03-26 19:01 ` [PATCH V3 09/25] perf/x86: Hybrid PMU support for event constraints kan.liang
2021-03-26 19:01 ` [PATCH V3 10/25] perf/x86: Hybrid PMU support for extra_regs kan.liang
2021-03-26 19:01 ` [PATCH V3 11/25] perf/x86/intel: Factor out intel_pmu_check_num_counters kan.liang
2021-03-26 19:01 ` [PATCH V3 12/25] perf/x86/intel: Factor out intel_pmu_check_event_constraints kan.liang
2021-03-26 19:02 ` [PATCH V3 13/25] perf/x86/intel: Factor out intel_pmu_check_extra_regs kan.liang
2021-03-26 19:02 ` [PATCH V3 14/25] perf/x86: Remove temporary pmu assignment in event_init kan.liang
2021-03-26 19:02 ` [PATCH V3 15/25] perf/x86: Factor out x86_pmu_show_pmu_cap kan.liang
2021-03-26 19:02 ` [PATCH V3 16/25] perf/x86: Register hybrid PMUs kan.liang
2021-03-26 19:02 ` [PATCH V3 17/25] perf/x86: Add structures for the attributes of Hybrid PMUs kan.liang
2021-03-26 19:02 ` [PATCH V3 18/25] perf/x86/intel: Add attr_update for " kan.liang
2021-03-26 19:02 ` [PATCH V3 19/25] perf/x86: Support filter_match callback kan.liang
2021-03-26 19:02 ` [PATCH V3 20/25] perf/x86/intel: Add Alder Lake Hybrid support kan.liang
2021-03-26 19:02 ` [PATCH V3 21/25] perf: Introduce PERF_TYPE_HARDWARE_PMU and PERF_TYPE_HW_CACHE_PMU kan.liang
2021-03-26 19:02 ` [PATCH V3 22/25] perf/x86/intel/uncore: Add Alder Lake support kan.liang
2021-03-26 19:02 ` kan.liang [this message]
2021-03-26 19:02 ` [PATCH V3 24/25] perf/x86/cstate: Add Alder Lake CPU support kan.liang
2021-03-26 19:02 ` [PATCH V3 25/25] perf/x86/rapl: Add support for Intel Alder Lake kan.liang
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1616785332-165261-24-git-send-email-kan.liang@linux.intel.com \
--to=kan.liang@linux.intel.com \
--cc=acme@kernel.org \
--cc=adrian.hunter@intel.com \
--cc=ak@linux.intel.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=bp@alien8.de \
--cc=jolsa@redhat.com \
--cc=linux-kernel@vger.kernel.org \
--cc=mingo@kernel.org \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=tglx@linutronix.de \
--cc=yao.jin@linux.intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox