From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.2 required=3.0 tests=BAYES_00,DATE_IN_PAST_06_12, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E592C433ED for ; Thu, 15 Apr 2021 00:02:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 608F7611AD for ; Thu, 15 Apr 2021 00:02:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230452AbhDOACd (ORCPT ); Wed, 14 Apr 2021 20:02:33 -0400 Received: from mga01.intel.com ([192.55.52.88]:63049 "EHLO mga01.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230346AbhDOACc (ORCPT ); Wed, 14 Apr 2021 20:02:32 -0400 IronPort-SDR: FpM/KF6LHKJj0bdY10CI5Rn2n7yZ0/xeMAsU2/mKPRv5i+jIUNQzSmtIMIVqEf5Hf9IRfLPXFF gnAkFWBoPpHA== X-IronPort-AV: E=McAfee;i="6200,9189,9954"; a="215260300" X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="215260300" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Apr 2021 17:02:10 -0700 IronPort-SDR: gzweu2Lq5EAvp9QHVB6sL26GIzb2BZtG7XWDtK1xA0XGSL/+zEmRcydXarQGaH9wUmifsSw0d6 UA7HwCMmlKmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.82,223,1613462400"; d="scan'208";a="461415805" Received: from otc-wp-03.jf.intel.com ([10.54.39.79]) by orsmga001.jf.intel.com with ESMTP; 14 Apr 2021 17:02:10 -0700 From: Jacob Pan To: LKML , iommu@lists.linux-foundation.org, Joerg Roedel , "Lu Baolu" , Jean-Philippe Brucker Cc: Yi Liu , Raj Ashok , "Tian, Kevin" , Jason Gunthorpe , Dave Jiang , wangzhou1@hisilicon.com, zhangfei.gao@linaro.org, vkoul@kernel.org, Jacob Pan Subject: [PATCH v2 0/2] Simplify and restrict IOMMU SVA APIs Date: Wed, 14 Apr 2021 08:27:55 -0700 Message-Id: <1618414077-28808-1-git-send-email-jacob.jun.pan@linux.intel.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A couple of small changes to simplify and restrict SVA APIs. The motivation is to make PASID allocation palatable for cgroup consumptions. Misc cgroup is merged for v5.13, it can be extended for IOASID as another scalar resource. I have not tested on ARM platforms due to availability. Would appreciate if someone could help with the testing on ARM. Thanks, Jacob ChangeLog: V2 - retained mm argument in iommu_sva_alloc_pasid() - keep generic supervisor flag separated from vt-d's SRE - move flag declaration out of CONFIG_IOMMU_API Jacob Pan (2): iommu/sva: Tighten SVA bind API with explicit flags iommu/sva: Remove mm parameter from SVA bind API drivers/dma/idxd/cdev.c | 2 +- drivers/dma/idxd/init.c | 7 +++--- .../iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c | 5 +++- drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 4 ++-- drivers/iommu/intel/svm.c | 14 ++++------- drivers/iommu/iommu-sva-lib.c | 11 +++++---- drivers/iommu/iommu.c | 23 +++++++++++++------ drivers/misc/uacce/uacce.c | 2 +- include/linux/intel-iommu.h | 2 +- include/linux/intel-svm.h | 17 ++------------ include/linux/iommu.h | 20 ++++++++++++---- 11 files changed, 57 insertions(+), 50 deletions(-) base-commit: e49d033bddf5b565044e2abe4241353959bc9120 -- 2.25.1