Re: [PATCH v5 2/4] arm64: dts: qcom: sc7280: Add PCIe and PHY related nodes

Prasad Malisetty
2021-08-17T06:00:50Z

On 2021-08-12 11:37, Manivannan Sadhasivam wrote:
> On Tue, Aug 10, 2021 at 09:38:34AM +0530, Prasad Malisetty wrote:
>> Add PCIe controller and PHY nodes for sc7280 SOC.
>>
>> Signed-off-by: Prasad Malisetty <pmaliset@codeaurora.org>
>> ---
>> arch/arm64/boot/dts/qcom/sc7280.dtsi | 126
>> +++++++++++++++++++++++++++++++++++
>> 1 file changed, 126 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> index 53a21d0..4500d88 100644
>> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
>> @@ -16,6 +16,7 @@
>> #include <dt-bindings/reset/qcom,sdm845-pdc.h>
>> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>> #include <dt-bindings/thermal/thermal.h>
>> +#include <dt-bindings/gpio/gpio.h>
>>
>> / {
>> interrupt-parent = <&intc>;
>> @@ -586,6 +587,119 @@
>> qcom,bcm-voters = <&apps_bcm_voter>;
>> };
>>
>> + pcie1: pci@1c08000 {
>> + compatible = "qcom,pcie-sc7280", "qcom,pcie-sm8250",
>> "snps,dw-pcie";
>
> Why 2 fallbacks? Fallbacks are meant to be used when the "fallback"
> compatible
> driver can fully support the hw. In this case, neither
> "qcom,pcie-sm8250" nor "snps,dw-pcie"
> can work properly, right?
>
> I did the same mistake for SM8250 though... But please get rid of them.
>
Hi Mani,

Thanks for your review and comments.

Sure I agree, will remove one of the fallbacks and update the changes in
next version.

Thanks
-Prasad

>> + reg = <0 0x01c08000 0 0x3000>,
>> + <0 0x40000000 0 0xf1d>,
>> + <0 0x40000f20 0 0xa8>,
>> + <0 0x40001000 0 0x1000>,
>> + <0 0x40100000 0 0x100000>;
>> +
>> + reg-names = "parf", "dbi", "elbi", "atu", "config";
>> + device_type = "pci";
>> + linux,pci-domain = <1>;
>> + bus-range = <0x00 0xff>;
>> + num-lanes = <2>;
>> + pipe-clk-source-switch;
>
> Did you document this property in binding? You need to add "qcom"
> prefix since
> this is a qcom specific one and not a generic PCI property.
>
> Thanks,
> Mani
>

I haven't document this property, missed it in v5. once this change is
finalized
I will update it next version.

>> +
>> + #address-cells = <3>;
>> + #size-cells = <2>;
>> +
>> + ranges = <0x01000000 0x0 0x40200000 0x0 0x40200000 0x0 0x100000>,
>> + <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>;
>> +
>> + interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>;
>> + interrupt-names = "msi";
>> + #interrupt-cells = <1>;
>> + interrupt-map-mask = <0 0 0 0x7>;
>> + interrupt-map = <0 0 0 1 &intc 0 434 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 2 &intc 0 435 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 3 &intc 0 438 IRQ_TYPE_LEVEL_HIGH>,
>> + <0 0 0 4 &intc 0 439 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>,
>> + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>,
>> + <&pcie1_lane 0>,
>> + <&rpmhcc RPMH_CXO_CLK>,
>> + <&gcc GCC_PCIE_1_AUX_CLK>,
>> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
>> + <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
>> + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>,
>> + <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
>> + <&gcc GCC_DDRSS_PCIE_SF_CLK>;
>> +
>> + clock-names = "pipe",
>> + "pipe_mux",
>> + "phy_pipe",
>> + "ref",
>> + "aux",
>> + "cfg",
>> + "bus_master",
>> + "bus_slave",
>> + "slave_q2a",
>> + "tbu",
>> + "ddrss_sf_tbu";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
>> + assigned-clock-rates = <19200000>;
>> +
>> + resets = <&gcc GCC_PCIE_1_BCR>;
>> + reset-names = "pci";
>> +
>> + power-domains = <&gcc GCC_PCIE_1_GDSC>;
>> +
>> + phys = <&pcie1_lane>;
>> + phy-names = "pciephy";
>> +
>> + perst-gpio = <&tlmm 2 GPIO_ACTIVE_LOW>;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pcie1_default_state>;
>> +
>> + iommus = <&apps_smmu 0x1c80 0x1>;
>> +
>> + iommu-map = <0x0 &apps_smmu 0x1c80 0x1>,
>> + <0x100 &apps_smmu 0x1c81 0x1>;
>> +
>> + status = "disabled";
>> + };
>> +
>> + pcie1_phy: phy@1c0e000 {
>> + compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy";
>> + reg = <0 0x01c0e000 0 0x1c0>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> + clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
>> + <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
>> + <&gcc GCC_PCIE_CLKREF_EN>,
>> + <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
>> + clock-names = "aux", "cfg_ahb", "ref", "refgen";
>> +
>> + resets = <&gcc GCC_PCIE_1_PHY_BCR>;
>> + reset-names = "phy";
>> +
>> + assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>;
>> + assigned-clock-rates = <100000000>;
>> +
>> + status = "disabled";
>> +
>> + pcie1_lane: lanes@1c0e200 {
>> + reg = <0 0x01c0e200 0 0x170>,
>> + <0 0x01c0e400 0 0x200>,
>> + <0 0x01c0ea00 0 0x1f0>,
>> + <0 0x01c0e600 0 0x170>,
>> + <0 0x01c0e800 0 0x200>,
>> + <0 0x01c0ee00 0 0xf4>;
>> + clocks = <&rpmhcc RPMH_CXO_CLK>;
>> + clock-names = "pipe0";
>> +
>> + #phy-cells = <0>;
>> + #clock-cells = <1>;
>> + clock-output-names = "pcie_1_pipe_clk";
>> + };
>> + };
>> +
>> ipa: ipa@1e40000 {
>> compatible = "qcom,sc7280-ipa";
>>
>> @@ -1598,6 +1712,18 @@
>> bias-bus-hold;
>> };
>> };
>> +
>> + pcie1_default_state: pcie1-default-state {
>> + clkreq {
>> + pins = "gpio79";
>> + function = "pcie1_clkreqn";
>> + };
>> +
>> + wake-n {
>> + pins = "gpio3";
>> + function = "gpio";
>> + };
>> + };
>> };
>>
>> apps_smmu: iommu@15000000 {
>> --
>> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora
>> Forum,
>> a Linux Foundation Collaborative Project
>>