From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B417BC433FE for ; Wed, 20 Oct 2021 13:59:20 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9AAAD60EB2 for ; Wed, 20 Oct 2021 13:59:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230373AbhJTOBe (ORCPT ); Wed, 20 Oct 2021 10:01:34 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:62668 "EHLO alexa-out.qualcomm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230031AbhJTOBc (ORCPT ); Wed, 20 Oct 2021 10:01:32 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1634738358; x=1666274358; h=from:to:cc:subject:date:message-id:in-reply-to: references; bh=VOl4fmMnTq/x2gytWdzrYoGSIQBnGN6dsI5IlLpay/w=; b=P8/GRkJWHkBBHiX7c/fqJM+xWthisJYywk6NNX8QbiqEm4k2vWk8yPi6 0z8z5WVLrR0+M36VMVkOrrf8QxpMrQ+8Bdx7ABz2ezc0I2tn3bbGYhizA hIcWt/7dolGdYR8lhi7zULbzzbcecRRVHDDLiJr8pULTTkRHKdVUpgDsl I=; Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 20 Oct 2021 06:59:17 -0700 X-QCInternal: smtphost Received: from ironmsg02-blr.qualcomm.com ([10.86.208.131]) by ironmsg-lv-alpha.qualcomm.com with ESMTP/TLS/AES256-SHA; 20 Oct 2021 06:59:15 -0700 X-QCInternal: smtphost Received: from mkrishn-linux.qualcomm.com ([10.204.66.35]) by ironmsg02-blr.qualcomm.com with ESMTP; 20 Oct 2021 19:28:59 +0530 Received: by mkrishn-linux.qualcomm.com (Postfix, from userid 438394) id 023FA2224E; Wed, 20 Oct 2021 19:28:57 +0530 (IST) From: Krishna Manikandan To: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krishna Manikandan , kalyan_t@codeaurora.org, sbillaka@codeaurora.org, abhinavk@codeaurora.org, robdclark@gmail.com, swboyd@chromium.org, bjorn.andersson@linaro.org, khsieh@codeaurora.org, rajeevny@codeaurora.org, freedreno@lists.freedesktop.org, dri-devel@lists.freedesktop.org, robh+dt@kernel.org, Rajeev Nandan Subject: [PATCH v2 3/4] arm64: dts: qcom: sc7280: Add DSI display nodes Date: Wed, 20 Oct 2021 19:28:52 +0530 Message-Id: <1634738333-3916-3-git-send-email-quic_mkrishn@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1634738333-3916-1-git-send-email-quic_mkrishn@quicinc.com> References: <1634738333-3916-1-git-send-email-quic_mkrishn@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Add DSI controller and PHY nodes for sc7280. Signed-off-by: Rajeev Nandan Signed-off-by: Krishna Manikandan Reviewed-by: Matthias Kaehlcke Changes in v2: - Drop flags from interrupts (Stephen Boyd) - Rename dsi-opp-table (Stephen Boyd) - Rename dsi phy node (Stephen Boyd) --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 101 +++++++++++++++++++++++++++++++++++ 1 file changed, 101 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi index 4ee7f2f..dd35882 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2652,6 +2652,18 @@ status = "disabled"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + }; + mdp_opp_table: opp-table { compatible = "operating-points-v2"; @@ -2676,6 +2688,95 @@ }; }; }; + + dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC7280_CX>; + + phys = <&dsi_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi_phy: phy@ae94400 { + compatible = "qcom,sc7280-dsi-phy-7nm"; + reg = <0 0x0ae94400 0 0x200>, + <0 0x0ae94600 0 0x280>, + <0 0x0ae94900 0 0x280>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; }; pdc: interrupt-controller@b220000 { -- 2.7.4