From: Odelu Kukatla <okukatla@codeaurora.org>
To: georgi.djakov@linaro.org, bjorn.andersson@linaro.org,
evgreen@google.com, Andy Gross <agross@kernel.org>,
Georgi Djakov <djakov@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org,
linux-kernel@vger.kernel.org
Cc: sboyd@kernel.org, mdtipton@codeaurora.org, sibis@codeaurora.org,
saravanak@google.com, okukatla@codeaurora.org,
seansw@qti.qualcomm.com, elder@linaro.org,
linux-arm-msm-owner@vger.kernel.org
Subject: [v8 2/3] interconnect: qcom: Add EPSS L3 support on SC7280
Date: Thu, 21 Oct 2021 16:10:56 +0530 [thread overview]
Message-ID: <1634812857-10676-3-git-send-email-okukatla@codeaurora.org> (raw)
In-Reply-To: <1634812857-10676-1-git-send-email-okukatla@codeaurora.org>
Add Epoch Subsystem (EPSS) L3 interconnect provider support on
SC7280 SoCs.
Signed-off-by: Odelu Kukatla <okukatla@codeaurora.org>
---
drivers/interconnect/qcom/osm-l3.c | 20 +++++++++++++++++++-
drivers/interconnect/qcom/sc7280.h | 2 ++
2 files changed, 21 insertions(+), 1 deletion(-)
diff --git a/drivers/interconnect/qcom/osm-l3.c b/drivers/interconnect/qcom/osm-l3.c
index c7af143..eec1309 100644
--- a/drivers/interconnect/qcom/osm-l3.c
+++ b/drivers/interconnect/qcom/osm-l3.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0
/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/bitfield.h>
@@ -15,6 +15,7 @@
#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include "sc7180.h"
+#include "sc7280.h"
#include "sc8180x.h"
#include "sdm845.h"
#include "sm8150.h"
@@ -114,6 +115,22 @@ static const struct qcom_osm_l3_desc sc7180_icc_osm_l3 = {
.reg_perf_state = OSM_REG_PERF_STATE,
};
+DEFINE_QNODE(sc7280_epss_apps_l3, SC7280_MASTER_EPSS_L3_APPS, 32, SC7280_SLAVE_EPSS_L3);
+DEFINE_QNODE(sc7280_epss_l3, SC7280_SLAVE_EPSS_L3, 32);
+
+static const struct qcom_osm_l3_node *sc7280_epss_l3_nodes[] = {
+ [MASTER_EPSS_L3_APPS] = &sc7280_epss_apps_l3,
+ [SLAVE_EPSS_L3_SHARED] = &sc7280_epss_l3,
+};
+
+static const struct qcom_osm_l3_desc sc7280_icc_epss_l3 = {
+ .nodes = sc7280_epss_l3_nodes,
+ .num_nodes = ARRAY_SIZE(sc7280_epss_l3_nodes),
+ .lut_row_size = EPSS_LUT_ROW_SIZE,
+ .reg_freq_lut = EPSS_REG_FREQ_LUT,
+ .reg_perf_state = EPSS_REG_PERF_STATE,
+};
+
DEFINE_QNODE(sc8180x_osm_apps_l3, SC8180X_MASTER_OSM_L3_APPS, 32, SC8180X_SLAVE_OSM_L3);
DEFINE_QNODE(sc8180x_osm_l3, SC8180X_SLAVE_OSM_L3, 32);
@@ -326,6 +343,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
static const struct of_device_id osm_l3_of_match[] = {
{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
+ { .compatible = "qcom,sc7280-epss-l3", .data = &sc7280_icc_epss_l3 },
{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
{ .compatible = "qcom,sm8150-osm-l3", .data = &sm8150_icc_osm_l3 },
{ .compatible = "qcom,sc8180x-osm-l3", .data = &sc8180x_icc_osm_l3 },
diff --git a/drivers/interconnect/qcom/sc7280.h b/drivers/interconnect/qcom/sc7280.h
index 175e400..1fb9839 100644
--- a/drivers/interconnect/qcom/sc7280.h
+++ b/drivers/interconnect/qcom/sc7280.h
@@ -150,5 +150,7 @@
#define SC7280_SLAVE_PCIE_1 139
#define SC7280_SLAVE_QDSS_STM 140
#define SC7280_SLAVE_TCU 141
+#define SC7280_MASTER_EPSS_L3_APPS 142
+#define SC7280_SLAVE_EPSS_L3 143
#endif
--
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
next prev parent reply other threads:[~2021-10-21 10:41 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-21 10:40 [v8 0/3] Add L3 provider support for SC7280 Odelu Kukatla
2021-10-21 10:40 ` [v8 1/3] dt-bindings: interconnect: Add EPSS L3 DT binding on SC7280 Odelu Kukatla
2021-10-27 16:59 ` Rob Herring
2021-10-28 22:13 ` Stephen Boyd
2021-10-21 10:40 ` Odelu Kukatla [this message]
2021-10-28 22:13 ` [v8 2/3] interconnect: qcom: Add EPSS L3 support " Stephen Boyd
2021-11-18 20:53 ` Bjorn Andersson
2021-11-22 15:25 ` Georgi Djakov
2021-10-21 10:40 ` [v8 3/3] arm64: dts: qcom: sc7280: Add EPSS L3 interconnect provider Odelu Kukatla
2021-10-28 22:14 ` Stephen Boyd
2021-10-28 23:27 ` Bjorn Andersson
2021-11-01 13:39 ` okukatla
2021-11-22 15:25 ` Georgi Djakov
2022-02-24 20:54 ` (subset) " Bjorn Andersson
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=1634812857-10676-3-git-send-email-okukatla@codeaurora.org \
--to=okukatla@codeaurora.org \
--cc=agross@kernel.org \
--cc=bjorn.andersson@linaro.org \
--cc=djakov@kernel.org \
--cc=elder@linaro.org \
--cc=evgreen@google.com \
--cc=georgi.djakov@linaro.org \
--cc=linux-arm-msm-owner@vger.kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-pm@vger.kernel.org \
--cc=mdtipton@codeaurora.org \
--cc=saravanak@google.com \
--cc=sboyd@kernel.org \
--cc=seansw@qti.qualcomm.com \
--cc=sibis@codeaurora.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox