[PATCH 0/2] ASoC: rt9120: Fix settings and add rt9120s compatibility

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* [PATCH 0/2] ASoC: rt9120: Fix settings and add rt9120s compatibility
@ 2021-11-09  6:23 cy_huang
  2021-11-09  6:23 ` [PATCH 1/2] ASoC: rt9120: Update internal setting and fix auto sync problem cy_huang
  2021-11-09  6:23 ` [PATCH 2/2] ASoC: rt9120: Add the compatibility with rt9120s cy_huang
  0 siblings, 2 replies; 5+ messages in thread
From: cy_huang @ 2021-11-09  6:23 UTC (permalink / raw)
  To: broonie, perex, tiwai
  Cc: oder_chiou, lgirdwood, alsa-devel, linux-kernel, cy_huang,
	allen_lin

From: ChiYuan Huang <cy_huang@richtek.com>

This patch series is to fix settings and add rt9120s compatibility

ChiYuan Huang (2):
  ASoC: rt9120: Update internal setting and fix auto sync problem
  ASoC: rt9120: Add the compatibility with rt9120s

 sound/soc/codecs/rt9120.c | 59 +++++++++++++++++++++++++++++++++++++++--------
 1 file changed, 49 insertions(+), 10 deletions(-)

-- 
2.7.4


^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 1/2] ASoC: rt9120: Update internal setting and fix auto sync problem
  2021-11-09  6:23 [PATCH 0/2] ASoC: rt9120: Fix settings and add rt9120s compatibility cy_huang
@ 2021-11-09  6:23 ` cy_huang
  2021-11-09 13:26   ` Mark Brown
  2021-11-09  6:23 ` [PATCH 2/2] ASoC: rt9120: Add the compatibility with rt9120s cy_huang
  1 sibling, 1 reply; 5+ messages in thread
From: cy_huang @ 2021-11-09  6:23 UTC (permalink / raw)
  To: broonie, perex, tiwai
  Cc: oder_chiou, lgirdwood, alsa-devel, linux-kernel, cy_huang,
	allen_lin

From: ChiYuan Huang <cy_huang@richtek.com>

- Update internal setting to fix issue.
- Disable auto sync if fs is divided by 48.

Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
---
 sound/soc/codecs/rt9120.c | 28 +++++++++++++++++++++-------
 1 file changed, 21 insertions(+), 7 deletions(-)

diff --git a/sound/soc/codecs/rt9120.c b/sound/soc/codecs/rt9120.c
index f957498..d007d00 100644
--- a/sound/soc/codecs/rt9120.c
+++ b/sound/soc/codecs/rt9120.c
@@ -26,6 +26,7 @@
 #define RT9120_REG_INTERNAL0	0x65
 #define RT9120_REG_INTERNAL1	0x69
 #define RT9120_REG_UVPOPT	0x6C
+#define RT9120_REG_DIGCFG	0xF8
 
 #define RT9120_VID_MASK		GENMASK(15, 8)
 #define RT9120_SWRST_MASK	BIT(7)
@@ -46,6 +47,7 @@
 #define RT9120_CFG_WORDLEN_24	24
 #define RT9120_CFG_WORDLEN_32	32
 #define RT9120_DVDD_UVSEL_MASK	GENMASK(5, 4)
+#define RT9120_AUTOSYNC_MASK	BIT(6)
 
 #define RT9120_VENDOR_ID	0x4200
 #define RT9120_RESET_WAITMS	20
@@ -149,8 +151,7 @@ static int rt9120_codec_probe(struct snd_soc_component *comp)
 	snd_soc_component_init_regmap(comp, data->regmap);
 
 	/* Internal setting */
-	snd_soc_component_write(comp, RT9120_REG_INTERNAL1, 0x03);
-	snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x69);
+	snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
 	return 0;
 }
 
@@ -201,8 +202,8 @@ static int rt9120_hw_params(struct snd_pcm_substream *substream,
 			    struct snd_soc_dai *dai)
 {
 	struct snd_soc_component *comp = dai->component;
-	unsigned int param_width, param_slot_width;
-	int width;
+	unsigned int param_width, param_slot_width, auto_sync;
+	int width, fs;
 
 	switch (width = params_width(param)) {
 	case 16:
@@ -240,6 +241,17 @@ static int rt9120_hw_params(struct snd_pcm_substream *substream,
 
 	snd_soc_component_update_bits(comp, RT9120_REG_I2SWL,
 				      RT9120_AUDWL_MASK, param_slot_width);
+
+	fs = width * params_channels(param);
+	/* If fs is divided by 48, disable auto sync */
+	if (fs % 48 == 0)
+		auto_sync = 0;
+	else
+		auto_sync = RT9120_AUTOSYNC_MASK;
+
+	snd_soc_component_update_bits(comp, RT9120_REG_DIGCFG,
+				      RT9120_AUTOSYNC_MASK, auto_sync);
+
 	return 0;
 }
 
@@ -281,7 +293,8 @@ static const struct regmap_range rt9120_rd_yes_ranges[] = {
 	regmap_reg_range(0x3A, 0x40),
 	regmap_reg_range(0x65, 0x65),
 	regmap_reg_range(0x69, 0x69),
-	regmap_reg_range(0x6C, 0x6C)
+	regmap_reg_range(0x6C, 0x6C),
+	regmap_reg_range(0xF8, 0xF8)
 };
 
 static const struct regmap_access_table rt9120_rd_table = {
@@ -299,7 +312,8 @@ static const struct regmap_range rt9120_wr_yes_ranges[] = {
 	regmap_reg_range(0x40, 0x40),
 	regmap_reg_range(0x65, 0x65),
 	regmap_reg_range(0x69, 0x69),
-	regmap_reg_range(0x6C, 0x6C)
+	regmap_reg_range(0x6C, 0x6C),
+	regmap_reg_range(0xF8, 0xF8)
 };
 
 static const struct regmap_access_table rt9120_wr_table = {
@@ -370,7 +384,7 @@ static int rt9120_reg_write(void *context, unsigned int reg, unsigned int val)
 static const struct regmap_config rt9120_regmap_config = {
 	.reg_bits = 8,
 	.val_bits = 32,
-	.max_register = RT9120_REG_UVPOPT,
+	.max_register = RT9120_REG_DIGCFG,
 
 	.reg_read = rt9120_reg_read,
 	.reg_write = rt9120_reg_write,
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/2] ASoC: rt9120: Update internal setting and fix auto sync problem
  2021-11-09  6:23 ` [PATCH 1/2] ASoC: rt9120: Update internal setting and fix auto sync problem cy_huang
@ 2021-11-09 13:26   ` Mark Brown
  2021-11-09 13:38     ` ChiYuan Huang
  0 siblings, 1 reply; 5+ messages in thread
From: Mark Brown @ 2021-11-09 13:26 UTC (permalink / raw)
  To: cy_huang
  Cc: perex, tiwai, oder_chiou, lgirdwood, alsa-devel, linux-kernel,
	cy_huang, allen_lin

[-- Attachment #1: Type: text/plain, Size: 541 bytes --]

On Tue, Nov 09, 2021 at 02:23:43PM +0800, cy_huang wrote:
> From: ChiYuan Huang <cy_huang@richtek.com>
> 
> - Update internal setting to fix issue.
> - Disable auto sync if fs is divided by 48.

Please submit one patch per change, each with a clear changelog, as
covered in SubmittingPatches.  This makes it much easier to review
things since it's easier to tell if the patch does what it was intended
to do.  When splitting patches up git gui can be helpful, you can stage
and unstage individual lines by right clicking on them.

[-- Attachment #2: signature.asc --]
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^ permalink raw reply	[flat|nested] 5+ messages in thread

* Re: [PATCH 1/2] ASoC: rt9120: Update internal setting and fix auto sync problem
  2021-11-09 13:26   ` Mark Brown
@ 2021-11-09 13:38     ` ChiYuan Huang
  0 siblings, 0 replies; 5+ messages in thread
From: ChiYuan Huang @ 2021-11-09 13:38 UTC (permalink / raw)
  To: Mark Brown
  Cc: perex, tiwai, oder_chiou, Liam Girdwood, alsa-devel, lkml,
	cy_huang, allen lin

Mark Brown <broonie@kernel.org> 於 2021年11月9日 週二 下午9:26寫道：
>
> On Tue, Nov 09, 2021 at 02:23:43PM +0800, cy_huang wrote:
> > From: ChiYuan Huang <cy_huang@richtek.com>
> >
> > - Update internal setting to fix issue.
> > - Disable auto sync if fs is divided by 48.
>
> Please submit one patch per change, each with a clear changelog, as
> covered in SubmittingPatches.  This makes it much easier to review
> things since it's easier to tell if the patch does what it was intended
> to do.  When splitting patches up git gui can be helpful, you can stage
> and unstage individual lines by right clicking on them.

OK, I'll split it with two changes to make it more clear.

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [PATCH 2/2] ASoC: rt9120: Add the compatibility with rt9120s
  2021-11-09  6:23 [PATCH 0/2] ASoC: rt9120: Fix settings and add rt9120s compatibility cy_huang
  2021-11-09  6:23 ` [PATCH 1/2] ASoC: rt9120: Update internal setting and fix auto sync problem cy_huang
@ 2021-11-09  6:23 ` cy_huang
  1 sibling, 0 replies; 5+ messages in thread
From: cy_huang @ 2021-11-09  6:23 UTC (permalink / raw)
  To: broonie, perex, tiwai
  Cc: oder_chiou, lgirdwood, alsa-devel, linux-kernel, cy_huang,
	allen_lin

From: ChiYuan Huang <cy_huang@richtek.com>

Use device id reg to be compatible with rt9120 and rt9120s.

Signed-off-by: ChiYuan Huang <cy_huang@richtek.com>
---
 sound/soc/codecs/rt9120.c | 33 +++++++++++++++++++++++++++++----
 1 file changed, 29 insertions(+), 4 deletions(-)

diff --git a/sound/soc/codecs/rt9120.c b/sound/soc/codecs/rt9120.c
index d007d00..6974705 100644
--- a/sound/soc/codecs/rt9120.c
+++ b/sound/soc/codecs/rt9120.c
@@ -1,6 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0
 
 #include <linux/bits.h>
+#include <linux/bitfield.h>
 #include <linux/delay.h>
 #include <linux/gpio/consumer.h>
 #include <linux/i2c.h>
@@ -23,6 +24,7 @@
 #define RT9120_REG_ERRRPT	0x10
 #define RT9120_REG_MSVOL	0x20
 #define RT9120_REG_SWRESET	0x40
+#define RT9120_REG_INTERCFG	0x63
 #define RT9120_REG_INTERNAL0	0x65
 #define RT9120_REG_INTERNAL1	0x69
 #define RT9120_REG_UVPOPT	0x6C
@@ -49,7 +51,8 @@
 #define RT9120_DVDD_UVSEL_MASK	GENMASK(5, 4)
 #define RT9120_AUTOSYNC_MASK	BIT(6)
 
-#define RT9120_VENDOR_ID	0x4200
+#define RT9120_VENDOR_ID	0x42
+#define RT9120S_VENDOR_ID	0x43
 #define RT9120_RESET_WAITMS	20
 #define RT9120_CHIPON_WAITMS	20
 #define RT9120_AMPON_WAITMS	50
@@ -63,9 +66,16 @@
 				 SNDRV_PCM_FMTBIT_S24_LE |\
 				 SNDRV_PCM_FMTBIT_S32_LE)
 
+enum {
+	CHIP_IDX_RT9120 = 0,
+	CHIP_IDX_RT9120S,
+	CHIP_IDX_MAX
+};
+
 struct rt9120_data {
 	struct device *dev;
 	struct regmap *regmap;
+	int chip_idx;
 };
 
 /* 11bit [min,max,step] = [-103.9375dB, 24dB, 0.0625dB] */
@@ -151,7 +161,12 @@ static int rt9120_codec_probe(struct snd_soc_component *comp)
 	snd_soc_component_init_regmap(comp, data->regmap);
 
 	/* Internal setting */
-	snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
+	if (data->chip_idx == CHIP_IDX_RT9120S) {
+		snd_soc_component_write(comp, RT9120_REG_INTERCFG, 0xde);
+		snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x66);
+	} else
+		snd_soc_component_write(comp, RT9120_REG_INTERNAL0, 0x04);
+
 	return 0;
 }
 
@@ -291,6 +306,7 @@ static const struct regmap_range rt9120_rd_yes_ranges[] = {
 	regmap_reg_range(0x20, 0x27),
 	regmap_reg_range(0x30, 0x38),
 	regmap_reg_range(0x3A, 0x40),
+	regmap_reg_range(0x63, 0x63),
 	regmap_reg_range(0x65, 0x65),
 	regmap_reg_range(0x69, 0x69),
 	regmap_reg_range(0x6C, 0x6C),
@@ -310,6 +326,7 @@ static const struct regmap_range rt9120_wr_yes_ranges[] = {
 	regmap_reg_range(0x30, 0x38),
 	regmap_reg_range(0x3A, 0x3D),
 	regmap_reg_range(0x40, 0x40),
+	regmap_reg_range(0x63, 0x63),
 	regmap_reg_range(0x65, 0x65),
 	regmap_reg_range(0x69, 0x69),
 	regmap_reg_range(0x6C, 0x6C),
@@ -402,8 +419,16 @@ static int rt9120_check_vendor_info(struct rt9120_data *data)
 	if (ret)
 		return ret;
 
-	if ((devid & RT9120_VID_MASK) != RT9120_VENDOR_ID) {
-		dev_err(data->dev, "DEVID not correct [0x%04x]\n", devid);
+	devid = FIELD_GET(RT9120_VID_MASK, devid);
+	switch (devid) {
+	case RT9120_VENDOR_ID:
+		data->chip_idx = CHIP_IDX_RT9120;
+		break;
+	case RT9120S_VENDOR_ID:
+		data->chip_idx = CHIP_IDX_RT9120S;
+		break;
+	default:
+		dev_err(data->dev, "DEVID not correct [0x%0x]\n", devid);
 		return -ENODEV;
 	}
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2021-11-09 13:39 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2021-11-09  6:23 [PATCH 0/2] ASoC: rt9120: Fix settings and add rt9120s compatibility cy_huang
2021-11-09  6:23 ` [PATCH 1/2] ASoC: rt9120: Update internal setting and fix auto sync problem cy_huang
2021-11-09 13:26   ` Mark Brown
2021-11-09 13:38     ` ChiYuan Huang
2021-11-09  6:23 ` [PATCH 2/2] ASoC: rt9120: Add the compatibility with rt9120s cy_huang

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