* [PATCH v9 1/3] firmware: qcom_scm: provide a read-modify-write function
2023-10-30 6:56 [PATCH v9 0/3] Misc SCM driver changes Mukesh Ojha
@ 2023-10-30 6:56 ` Mukesh Ojha
2023-10-30 6:56 ` [PATCH v9 2/3] firmware: scm: Modify only the download bits in TCSR register Mukesh Ojha
2023-10-30 6:56 ` [PATCH v9 3/3] pinctrl: qcom: Use qcom_scm_io_rmw() function Mukesh Ojha
2 siblings, 0 replies; 4+ messages in thread
From: Mukesh Ojha @ 2023-10-30 6:56 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, linus.walleij
Cc: linux-arm-msm, linux-kernel, Mukesh Ojha
It was realized by Srinivas K. that there is a need of
read-modify-write scm exported function so that it can
be used by multiple clients.
Let's introduce qcom_scm_io_rmw() which masks out the bits
and write the passed value to that bit-offset.
Suggested-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Tested-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> # IPQ9574 and IPQ5332
---
drivers/firmware/qcom/qcom_scm.c | 26 ++++++++++++++++++++++++++
include/linux/firmware/qcom/qcom_scm.h | 1 +
2 files changed, 27 insertions(+)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 520de9b5633a..25549178a30f 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -19,6 +19,7 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
+#include <linux/spinlock.h>
#include <linux/reset-controller.h>
#include <linux/types.h>
@@ -41,6 +42,8 @@ struct qcom_scm {
int scm_vote_count;
u64 dload_mode_addr;
+ /* Atomic context only */
+ spinlock_t lock;
};
struct qcom_scm_current_perm_info {
@@ -481,6 +484,28 @@ static int qcom_scm_disable_sdi(void)
return ret ? : res.result[0];
}
+int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val)
+{
+ unsigned int old, new;
+ int ret;
+
+ if (!__scm)
+ return -EINVAL;
+
+ spin_lock(&__scm->lock);
+ ret = qcom_scm_io_readl(addr, &old);
+ if (ret)
+ goto unlock;
+
+ new = (old & ~mask) | (val & mask);
+
+ ret = qcom_scm_io_writel(addr, new);
+unlock:
+ spin_unlock(&__scm->lock);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(qcom_scm_io_rmw);
+
static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
{
struct qcom_scm_desc desc = {
@@ -1824,6 +1849,7 @@ static int qcom_scm_probe(struct platform_device *pdev)
return ret;
mutex_init(&scm->scm_bw_lock);
+ spin_lock_init(&scm->lock);
scm->path = devm_of_icc_get(&pdev->dev, NULL);
if (IS_ERR(scm->path))
diff --git a/include/linux/firmware/qcom/qcom_scm.h b/include/linux/firmware/qcom/qcom_scm.h
index ccaf28846054..3a8bb2e603b3 100644
--- a/include/linux/firmware/qcom/qcom_scm.h
+++ b/include/linux/firmware/qcom/qcom_scm.h
@@ -82,6 +82,7 @@ bool qcom_scm_pas_supported(u32 peripheral);
int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
+int qcom_scm_io_rmw(phys_addr_t addr, unsigned int mask, unsigned int val);
bool qcom_scm_restore_sec_cfg_available(void);
int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v9 2/3] firmware: scm: Modify only the download bits in TCSR register
2023-10-30 6:56 [PATCH v9 0/3] Misc SCM driver changes Mukesh Ojha
2023-10-30 6:56 ` [PATCH v9 1/3] firmware: qcom_scm: provide a read-modify-write function Mukesh Ojha
@ 2023-10-30 6:56 ` Mukesh Ojha
2023-10-30 6:56 ` [PATCH v9 3/3] pinctrl: qcom: Use qcom_scm_io_rmw() function Mukesh Ojha
2 siblings, 0 replies; 4+ messages in thread
From: Mukesh Ojha @ 2023-10-30 6:56 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, linus.walleij
Cc: linux-arm-msm, linux-kernel, Mukesh Ojha, Poovendhan Selvaraj
Crashdump collection is done based on DLOAD bits of TCSR register.
To retain other bits, scm driver need to read the register and
modify only the DLOAD bits, as other bits in TCSR may have their
own significance.
Co-developed-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Poovendhan Selvaraj <quic_poovendh@quicinc.com>
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Tested-by: Kathiravan Thirumoorthy <quic_kathirav@quicinc.com> # IPQ9574 and IPQ5332
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/firmware/qcom/qcom_scm.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/firmware/qcom/qcom_scm.c b/drivers/firmware/qcom/qcom_scm.c
index 25549178a30f..95f73a8c51d7 100644
--- a/drivers/firmware/qcom/qcom_scm.c
+++ b/drivers/firmware/qcom/qcom_scm.c
@@ -4,6 +4,8 @@
*/
#include <linux/arm-smccc.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
#include <linux/clk.h>
#include <linux/completion.h>
#include <linux/cpumask.h>
@@ -117,6 +119,12 @@ static const u8 qcom_scm_cpu_warm_bits[QCOM_SCM_BOOT_MAX_CPUS] = {
#define QCOM_SMC_WAITQ_FLAG_WAKE_ONE BIT(0)
#define QCOM_SMC_WAITQ_FLAG_WAKE_ALL BIT(1)
+#define QCOM_DLOAD_MASK GENMASK(5, 4)
+enum qcom_dload_mode {
+ QCOM_DLOAD_NODUMP = 0,
+ QCOM_DLOAD_FULLDUMP = 1,
+};
+
static const char * const qcom_scm_convention_names[] = {
[SMC_CONVENTION_UNKNOWN] = "unknown",
[SMC_CONVENTION_ARM_32] = "smc arm 32",
@@ -523,6 +531,7 @@ static int __qcom_scm_set_dload_mode(struct device *dev, bool enable)
static void qcom_scm_set_download_mode(bool enable)
{
+ u32 val = enable ? QCOM_DLOAD_FULLDUMP : QCOM_DLOAD_NODUMP;
bool avail;
int ret = 0;
@@ -532,8 +541,9 @@ static void qcom_scm_set_download_mode(bool enable)
if (avail) {
ret = __qcom_scm_set_dload_mode(__scm->dev, enable);
} else if (__scm->dload_mode_addr) {
- ret = qcom_scm_io_writel(__scm->dload_mode_addr,
- enable ? QCOM_SCM_BOOT_SET_DLOAD_MODE : 0);
+ ret = qcom_scm_io_rmw(__scm->dload_mode_addr,
+ QCOM_DLOAD_MASK,
+ FIELD_PREP(QCOM_DLOAD_MASK, val));
} else {
dev_err(__scm->dev,
"No available mechanism for setting download mode\n");
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH v9 3/3] pinctrl: qcom: Use qcom_scm_io_rmw() function
2023-10-30 6:56 [PATCH v9 0/3] Misc SCM driver changes Mukesh Ojha
2023-10-30 6:56 ` [PATCH v9 1/3] firmware: qcom_scm: provide a read-modify-write function Mukesh Ojha
2023-10-30 6:56 ` [PATCH v9 2/3] firmware: scm: Modify only the download bits in TCSR register Mukesh Ojha
@ 2023-10-30 6:56 ` Mukesh Ojha
2 siblings, 0 replies; 4+ messages in thread
From: Mukesh Ojha @ 2023-10-30 6:56 UTC (permalink / raw)
To: agross, andersson, konrad.dybcio, linus.walleij
Cc: linux-arm-msm, linux-kernel, Mukesh Ojha
Use qcom_scm_io_rmw() exported function in pinctrl-msm
driver.
Signed-off-by: Mukesh Ojha <quic_mojha@quicinc.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
---
drivers/pinctrl/qcom/pinctrl-msm.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-msm.c b/drivers/pinctrl/qcom/pinctrl-msm.c
index 395040346d0f..9323b916cd7c 100644
--- a/drivers/pinctrl/qcom/pinctrl-msm.c
+++ b/drivers/pinctrl/qcom/pinctrl-msm.c
@@ -1078,22 +1078,20 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
if (g->intr_target_width)
intr_target_mask = GENMASK(g->intr_target_width - 1, 0);
+ intr_target_mask <<= g->intr_target_bit;
if (pctrl->intr_target_use_scm) {
u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
int ret;
- qcom_scm_io_readl(addr, &val);
- val &= ~(intr_target_mask << g->intr_target_bit);
- val |= g->intr_target_kpss_val << g->intr_target_bit;
-
- ret = qcom_scm_io_writel(addr, val);
+ val = g->intr_target_kpss_val << g->intr_target_bit;
+ ret = qcom_scm_io_rmw(addr, intr_target_mask, val);
if (ret)
dev_err(pctrl->dev,
"Failed routing %lu interrupt to Apps proc",
d->hwirq);
} else {
val = msm_readl_intr_target(pctrl, g);
- val &= ~(intr_target_mask << g->intr_target_bit);
+ val &= ~intr_target_mask;
val |= g->intr_target_kpss_val << g->intr_target_bit;
msm_writel_intr_target(val, pctrl, g);
}
--
2.7.4
^ permalink raw reply related [flat|nested] 4+ messages in thread