[PATCH v2] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly

[PATCH v2] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly

[Yangyu Chen]

Previous commit dbfbda3bd6bf ("riscv: mm: update T-Head memory type
definitions") from patch [1] missed a `<` for bit shifting, result in
bit(61) does not set in _PAGE_NOCACHE_THEAD and leaves bit(0) set instead.
This patch get this fixed.

Changes since v1:
* reword commit message and add reviewed-by

Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]
Fixes: dbfbda3bd6bf ("riscv: mm: update T-Head memory type definitions")
Signed-off-by: Yangyu Chen <cyy@cyyself.name>
Reviewed-by: Guo Ren <guoren@kernel.org>
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
---
 arch/riscv/include/asm/pgtable-64.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
index b42017d76924..b99bd66107a6 100644
--- a/arch/riscv/include/asm/pgtable-64.h
+++ b/arch/riscv/include/asm/pgtable-64.h
@@ -136,7 +136,7 @@ enum napot_cont_order {
  * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
  */
 #define _PAGE_PMA_THEAD		((1UL << 62) | (1UL << 61) | (1UL << 60))
-#define _PAGE_NOCACHE_THEAD	((1UL < 61) | (1UL << 60))
+#define _PAGE_NOCACHE_THEAD	((1UL << 61) | (1UL << 60))
 #define _PAGE_IO_THEAD		((1UL << 63) | (1UL << 60))
 #define _PAGE_MTMASK_THEAD	(_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
 
-- 
2.43.0

Re: [PATCH v2] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly

[Alexandre Ghiti]

Hi Yangyu,

On Wed, Feb 21, 2024 at 4:04 AM Yangyu Chen <cyy@cyyself.name> wrote:
>
> Previous commit dbfbda3bd6bf ("riscv: mm: update T-Head memory type
> definitions") from patch [1] missed a `<` for bit shifting, result in
> bit(61) does not set in _PAGE_NOCACHE_THEAD and leaves bit(0) set instead.
> This patch get this fixed.
>
> Changes since v1:
> * reword commit message and add reviewed-by
>
> Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]
> Fixes: dbfbda3bd6bf ("riscv: mm: update T-Head memory type definitions")
> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
> Reviewed-by: Guo Ren <guoren@kernel.org>
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  arch/riscv/include/asm/pgtable-64.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
> index b42017d76924..b99bd66107a6 100644
> --- a/arch/riscv/include/asm/pgtable-64.h
> +++ b/arch/riscv/include/asm/pgtable-64.h
> @@ -136,7 +136,7 @@ enum napot_cont_order {
>   * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
>   */
>  #define _PAGE_PMA_THEAD                ((1UL << 62) | (1UL << 61) | (1UL << 60))
> -#define _PAGE_NOCACHE_THEAD    ((1UL < 61) | (1UL << 60))
> +#define _PAGE_NOCACHE_THEAD    ((1UL << 61) | (1UL << 60))
>  #define _PAGE_IO_THEAD         ((1UL << 63) | (1UL << 60))
>  #define _PAGE_MTMASK_THEAD     (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>
> --
> 2.43.0
>

I feel pretty confident on this one :)

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex

Re: [PATCH v2] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly

[Palmer Dabbelt]

On Wed, 21 Feb 2024 06:00:49 PST (-0800), alexghiti@rivosinc.com wrote:
> Hi Yangyu,
>
> On Wed, Feb 21, 2024 at 4:04 AM Yangyu Chen <cyy@cyyself.name> wrote:
>>
>> Previous commit dbfbda3bd6bf ("riscv: mm: update T-Head memory type
>> definitions") from patch [1] missed a `<` for bit shifting, result in
>> bit(61) does not set in _PAGE_NOCACHE_THEAD and leaves bit(0) set instead.
>> This patch get this fixed.
>>
>> Changes since v1:
>> * reword commit message and add reviewed-by
>>
>> Link: https://lore.kernel.org/linux-riscv/20230912072510.2510-1-jszhang@kernel.org/ [1]
>> Fixes: dbfbda3bd6bf ("riscv: mm: update T-Head memory type definitions")
>> Signed-off-by: Yangyu Chen <cyy@cyyself.name>
>> Reviewed-by: Guo Ren <guoren@kernel.org>
>> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
>> ---
>>  arch/riscv/include/asm/pgtable-64.h | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/arch/riscv/include/asm/pgtable-64.h b/arch/riscv/include/asm/pgtable-64.h
>> index b42017d76924..b99bd66107a6 100644
>> --- a/arch/riscv/include/asm/pgtable-64.h
>> +++ b/arch/riscv/include/asm/pgtable-64.h
>> @@ -136,7 +136,7 @@ enum napot_cont_order {
>>   * 10010 - IO   Strongly-ordered, Non-cacheable, Non-bufferable, Shareable, Non-trustable
>>   */
>>  #define _PAGE_PMA_THEAD                ((1UL << 62) | (1UL << 61) | (1UL << 60))
>> -#define _PAGE_NOCACHE_THEAD    ((1UL < 61) | (1UL << 60))
>> +#define _PAGE_NOCACHE_THEAD    ((1UL << 61) | (1UL << 60))
>>  #define _PAGE_IO_THEAD         ((1UL << 63) | (1UL << 60))
>>  #define _PAGE_MTMASK_THEAD     (_PAGE_PMA_THEAD | _PAGE_IO_THEAD | (1UL << 59))
>>
>> --
>> 2.43.0
>>
>
> I feel pretty confident on this one :)

Ya, sorry I missed it the first time around -- that's a bit embarassing 
;).  It should show up on fixes soon, just queued up behind some other 
patches but the tester is back alive so thing should be sane again.

> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
>
> Thanks,
>
> Alex

Re: [PATCH v2] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly

[patchwork-bot+linux-riscv]

Hello:

This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:

On Wed, 21 Feb 2024 11:02:31 +0800 you wrote:
> Previous commit dbfbda3bd6bf ("riscv: mm: update T-Head memory type
> definitions") from patch [1] missed a `<` for bit shifting, result in
> bit(61) does not set in _PAGE_NOCACHE_THEAD and leaves bit(0) set instead.
> This patch get this fixed.
> 
> Changes since v1:
> * reword commit message and add reviewed-by
> 
> [...]

Here is the summary with links:
  - [v2] riscv: mm: fix NOCACHE_THEAD does not set bit[61] correctly
    https://git.kernel.org/riscv/c/c21f01481860

You are awesome, thank you!
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