From: patchwork-bot+linux-riscv@kernel.org
To: Samuel Holland <samuel.holland@sifive.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
ajones@ventanamicro.com, linux-kernel@vger.kernel.org,
conor@kernel.org, alex@ghiti.fr, sorear@fastmail.com
Subject: Re: [PATCH -fixes v4 0/3] riscv: cbo.zero fixes
Date: Thu, 29 Feb 2024 22:10:34 +0000 [thread overview]
Message-ID: <170924463455.14902.4462676677426238717.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20240228065559.3434837-1-samuel.holland@sifive.com>
Hello:
This series was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Tue, 27 Feb 2024 22:55:32 -0800 you wrote:
> This series fixes a couple of issues related to using the cbo.zero
> instruction in userspace. The first patch fixes a bug where the wrong
> enable bit gets set if the kernel is running in M-mode. The remaining
> patches fix a bug where the enable bit gets reset to its default value
> after a nonretentive idle state. I have hardware which reproduces this:
>
> Before this series:
> $ tools/testing/selftests/riscv/hwprobe/cbo
> TAP version 13
> 1..3
> ok 1 Zicboz block size
> # Zicboz block size: 64
> Illegal instruction
>
> [...]
Here is the summary with links:
- [-fixes,v4,1/3] riscv: Fix enabling cbo.zero when running in M-mode
https://git.kernel.org/riscv/c/3fb3f7164edc
- [-fixes,v4,2/3] riscv: Add a custom ISA extension for the [ms]envcfg CSR
https://git.kernel.org/riscv/c/4774848fef60
- [-fixes,v4,3/3] riscv: Save/restore envcfg CSR during CPU suspend
https://git.kernel.org/riscv/c/05ab803d1ad8
You are awesome, thank you!
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prev parent reply other threads:[~2024-02-29 22:10 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-28 6:55 [PATCH -fixes v4 0/3] riscv: cbo.zero fixes Samuel Holland
2024-02-28 6:55 ` [PATCH -fixes v4 1/3] riscv: Fix enabling cbo.zero when running in M-mode Samuel Holland
2024-02-28 10:13 ` Conor Dooley
2024-02-28 6:55 ` [PATCH -fixes v4 2/3] riscv: Add a custom ISA extension for the [ms]envcfg CSR Samuel Holland
2024-02-28 10:12 ` Conor Dooley
2024-02-29 18:23 ` Palmer Dabbelt
2024-02-29 18:30 ` Conor Dooley
2024-02-29 23:40 ` Palmer Dabbelt
2024-02-28 13:23 ` Andrew Jones
2024-02-28 6:55 ` [PATCH -fixes v4 3/3] riscv: Save/restore envcfg CSR during CPU suspend Samuel Holland
2024-02-28 10:14 ` Conor Dooley
2024-02-28 13:27 ` Andrew Jones
2024-02-29 22:10 ` patchwork-bot+linux-riscv [this message]
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