From: patchwork-bot+linux-riscv@kernel.org
To: Jesse Taube <jesse@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, paul.walmsley@sifive.com,
palmer@dabbelt.com, aou@eecs.berkeley.edu,
conor.dooley@microchip.com, namcaov@gmail.com,
samitolvanen@google.com, charlie@rivosinc.com,
andy.chiu@sifive.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] RISC-V: fix vector insn load/store width mask
Date: Wed, 26 Jun 2024 14:21:19 +0000 [thread overview]
Message-ID: <171941167921.28907.4527273499430176135.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20240606182800.415831-1-jesse@rivosinc.com>
Hello:
This patch was applied to riscv/linux.git (fixes)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Thu, 6 Jun 2024 14:28:00 -0400 you wrote:
> RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits.
> Replace GENMASK(3, 0) with GENMASK(2, 0).
>
> Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap")
> Signed-off-by: Jesse Taube <jesse@rivosinc.com>
> ---
> arch/riscv/include/asm/insn.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Here is the summary with links:
- RISC-V: fix vector insn load/store width mask
https://git.kernel.org/riscv/c/04a2aef59cfe
You are awesome, thank you!
--
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prev parent reply other threads:[~2024-06-26 14:21 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-06 18:28 [PATCH] RISC-V: fix vector insn load/store width mask Jesse Taube
2024-06-06 18:59 ` Charlie Jenkins
2024-06-26 14:21 ` patchwork-bot+linux-riscv [this message]
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