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From: patchwork-bot+linux-riscv@kernel.org
To: Guo Ren <guoren@kernel.org>
Cc: linux-riscv@lists.infradead.org, paul.walmsley@sifive.com,
	palmer@dabbelt.com, bjorn@rivosinc.com, conor@kernel.org,
	leobras@redhat.com, alexghiti@rivosinc.com,
	christoph.muellner@vrull.eu, linux-kernel@vger.kernel.org,
	parri.andrea@gmail.com, ajones@ventanamicro.com,
	ericchancf@google.com, guoren@linux.alibaba.com
Subject: Re: [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs
Date: Thu, 27 Mar 2025 03:25:11 +0000	[thread overview]
Message-ID: <174304591124.1549280.8617793475801522686.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <20241217013910.1039923-1-guoren@kernel.org>

Hello:

This patch was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti@rivosinc.com>:

On Mon, 16 Dec 2024 20:39:10 -0500 you wrote:
> From: Guo Ren <guoren@linux.alibaba.com>
> 
> RISC-V code uses the queued spinlock implementation, which calls
> the macros smp_cond_load_acquire for one byte. So, complement the
> implementation of byte and halfword versions.
> 
> Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
> Signed-off-by: Guo Ren <guoren@kernel.org>
> Cc: Andrew Jones <ajones@ventanamicro.com>
> 
> [...]

Here is the summary with links:
  - [V2] riscv: Implement smp_cond_load8/16() with Zawrs
    https://git.kernel.org/riscv/c/d9708b1931fc

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html



      parent reply	other threads:[~2025-03-27  3:24 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-12-17  1:39 [PATCH V2] riscv: Implement smp_cond_load8/16() with Zawrs guoren
2024-12-17 13:03 ` Andrew Jones
2025-03-27  3:25 ` patchwork-bot+linux-riscv [this message]

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