[PATCH v1 0/9] x86/cpuid: Headers cleanup

[PATCH v1 0/9] x86/cpuid: Headers cleanup

[Ahmed S. Darwish]

Hi,

This is a CPUID headers cleanup series, on top of tip:x86/cpu.  It is a
precursor for the upcoming v2 of the CPUID parser:

    [PATCH v1 00/26] x86: Introduce centralized CPUID model
    https://lore.kernel.org/lkml/20250506050437.10264-1-darwi@linutronix.de

as suggested by Ingo here:

    https://lore.kernel.org/lkml/aBnSgu_JyEi8fvog@gmail.com

* Summary:

The current CPUID header structure is:

    include/asm/
    ├── cpuid
    │   ├── api.h
    │   ├── leaf_0x2_api.h
    │   └── types.h
    └── cpuid.h

Simplify it into:

    include/asm/
    ├── api.h
    └── types.h

Standardize the CPUID header namespace by enforcing a "cpuid_" prefix for
all exported symbols.  That is:

    have_cpuid_p()		➤	cpuid_feature()
    hypervisor_cpuid_base()	➤	cpuid_hypervisor_base()
    native_cpuid()		➤	cpuid_native()
    native_cpuid_REG()		➤	cpuid_native_REG()

Also rename:

    cpuid_get_leaf_0x2_regs()	➤	cpuid_leaf_0x2()

for consistency with the other <asm/cpuid/api.h> accessors that return
full CPUID register output; i.e., cpuid_leaf() and cpuid_subleaf().

Finally, rename:

    for_each_leaf_0x2_entry()   ➤	for_each_cpuid_0x2_desc()

to include "cpuid" in the iterator name, and since what is being iterated
upon is CPUID(0x2) cache and TLB "descriptos", not "entries".

* Testing:

- Basic one-by-one allyesconfig compilation

- Comparison of a before/after of below files:

  - /proc/cpuinfo
  - /sys/devices/system/cpu/
  - /sys/kernel/debug/x86/topo/
  - dmesg --notime | grep 'Last level [id]TLB entries'

Thanks!

8<--

Ahmed S. Darwish (9):
  x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>
  x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header
  x86/cpuid: Rename have_cpuid_p() to cpuid_feature()
  x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()
  x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()
  x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter
  x86/cpu: Rename CPUID(0x2) descriptors iterator parameter
  x86/cpuid: Rename native_cpuid() to cpuid_native()
  x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()

 arch/x86/boot/compressed/pgtable_64.c     |   4 +-
 arch/x86/boot/compressed/sev.c            |   8 +-
 arch/x86/coco/sev/core.c                  |   2 +-
 arch/x86/events/intel/pt.c                |   2 +-
 arch/x86/include/asm/acrn.h               |   2 +-
 arch/x86/include/asm/cpuid.h              |   9 --
 arch/x86/include/asm/cpuid/api.h          | 103 ++++++++++++++++++----
 arch/x86/include/asm/cpuid/leaf_0x2_api.h |  73 ---------------
 arch/x86/include/asm/cpuid/types.h        |   3 +-
 arch/x86/include/asm/microcode.h          |   2 +-
 arch/x86/include/asm/processor.h          |   2 +-
 arch/x86/include/asm/xen/hypervisor.h     |   2 +-
 arch/x86/kernel/acpi/cstate.c             |   2 +-
 arch/x86/kernel/amd_nb.c                  |   2 +-
 arch/x86/kernel/cpu/cacheinfo.c           |  18 ++--
 arch/x86/kernel/cpu/common.c              |  12 +--
 arch/x86/kernel/cpu/intel.c               |  16 ++--
 arch/x86/kernel/cpu/microcode/amd.c       |   2 +-
 arch/x86/kernel/cpu/microcode/core.c      |   8 +-
 arch/x86/kernel/cpu/microcode/intel.c     |   2 +-
 arch/x86/kernel/cpu/microcode/internal.h  |   4 +-
 arch/x86/kernel/fpu/xstate.c              |   2 +-
 arch/x86/kernel/head32.c                  |   2 +-
 arch/x86/kernel/hpet.c                    |   2 +-
 arch/x86/kernel/jailhouse.c               |   2 +-
 arch/x86/kernel/kvm.c                     |   2 +-
 arch/x86/kernel/paravirt.c                |   2 +-
 arch/x86/kernel/process.c                 |   2 +-
 arch/x86/kernel/smpboot.c                 |   2 +-
 arch/x86/kernel/tsc.c                     |   2 +-
 arch/x86/kvm/cpuid.c                      |   4 +-
 arch/x86/mm/mem_encrypt_identity.c        |   6 +-
 arch/x86/virt/svm/sev.c                   |   2 +-
 arch/x86/xen/enlighten_pv.c               |   6 +-
 drivers/acpi/acpi_pad.c                   |   2 +-
 drivers/dma/ioat/dca.c                    |   2 +-
 drivers/firmware/efi/libstub/x86-5lvl.c   |   4 +-
 drivers/idle/intel_idle.c                 |   2 +-
 drivers/platform/x86/intel/pmc/core.c     |   2 +-
 sound/soc/intel/avs/tgl.c                 |   2 +-
 40 files changed, 159 insertions(+), 169 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid.h
 delete mode 100644 arch/x86/include/asm/cpuid/leaf_0x2_api.h

base-commit: c1ab4ce3cb759f69fb9085a060e568b73e8f5cd8
-- 
2.49.0

[PATCH v1 1/9] x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>

[Ahmed S. Darwish]

Move all of the CPUID(0x2) APIs at <cpuid/leaf_0x2_api.h> into
<cpuid/api.h>, in order centralize all CPUID APIs into the latter.

While at it, separate the different CPUID leaf parsing APIs using
header comments like "CPUID(0xN) parsing: ".

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid.h              |  1 -
 arch/x86/include/asm/cpuid/api.h          | 75 ++++++++++++++++++++++-
 arch/x86/include/asm/cpuid/leaf_0x2_api.h | 73 ----------------------
 arch/x86/include/asm/cpuid/types.h        |  3 +-
 4 files changed, 75 insertions(+), 77 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid/leaf_0x2_api.h

diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h
index 585819331dc6..d5749b25fa10 100644
--- a/arch/x86/include/asm/cpuid.h
+++ b/arch/x86/include/asm/cpuid.h
@@ -4,6 +4,5 @@
 #define _ASM_X86_CPUID_H
 
 #include <asm/cpuid/api.h>
-#include <asm/cpuid/leaf_0x2_api.h>
 
 #endif /* _ASM_X86_CPUID_H */
diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index bf76a1706d02..ff8891a0b6c8 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -160,6 +160,10 @@ static inline void __cpuid_read_reg(u32 leaf, u32 subleaf,
 	__cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg));	\
 }
 
+/*
+ * Hypervisor-related APIs:
+ */
+
 static __always_inline bool cpuid_function_is_indexed(u32 function)
 {
 	switch (function) {
@@ -208,7 +212,76 @@ static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves)
 }
 
 /*
- * CPUID(0x80000006) parsing helpers
+ * CPUID(0x2) parsing:
+ */
+
+/**
+ * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
+ * @regs:	Output parameter
+ *
+ * Query CPUID leaf 0x2 and store its output in @regs.	Force set any
+ * invalid 1-byte descriptor returned by the hardware to zero (the NULL
+ * cache/TLB descriptor) before returning it to the caller.
+ *
+ * Use for_each_leaf_0x2_entry() to iterate over the register output in
+ * parsed form.
+ */
+static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
+{
+	cpuid_leaf(0x2, regs);
+
+	/*
+	 * All Intel CPUs must report an iteration count of 1.	In case
+	 * of bogus hardware, treat all returned descriptors as NULL.
+	 */
+	if (regs->desc[0] != 0x01) {
+		for (int i = 0; i < 4; i++)
+			regs->regv[i] = 0;
+		return;
+	}
+
+	/*
+	 * The most significant bit (MSB) of each register must be clear.
+	 * If a register is invalid, replace its descriptors with NULL.
+	 */
+	for (int i = 0; i < 4; i++) {
+		if (regs->reg[i].invalid)
+			regs->regv[i] = 0;
+	}
+}
+
+/**
+ * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
+ * @regs:   Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
+ * @__ptr:  u8 pointer, for macro internal use only
+ * @entry:  Pointer to parsed descriptor information at each iteration
+ *
+ * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
+ * @regs.  Provide the parsed information for each descriptor through @entry.
+ *
+ * To handle cache-specific descriptors, switch on @entry->c_type.  For TLB
+ * descriptors, switch on @entry->t_type.
+ *
+ * Example usage for cache descriptors::
+ *
+ *	const struct leaf_0x2_table *entry;
+ *	union leaf_0x2_regs regs;
+ *	u8 *ptr;
+ *
+ *	cpuid_get_leaf_0x2_regs(&regs);
+ *	for_each_leaf_0x2_entry(regs, ptr, entry) {
+ *		switch (entry->c_type) {
+ *			...
+ *		}
+ *	}
+ */
+#define for_each_leaf_0x2_entry(regs, __ptr, entry)				\
+	for (__ptr = &(regs).desc[1];						\
+	     __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]);	\
+	     __ptr++)
+
+/*
+ * CPUID(0x80000006) parsing:
  */
 
 static inline bool cpuid_amd_hygon_has_l3_cache(void)
diff --git a/arch/x86/include/asm/cpuid/leaf_0x2_api.h b/arch/x86/include/asm/cpuid/leaf_0x2_api.h
deleted file mode 100644
index 09fa3070b271..000000000000
--- a/arch/x86/include/asm/cpuid/leaf_0x2_api.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_X86_CPUID_LEAF_0x2_API_H
-#define _ASM_X86_CPUID_LEAF_0x2_API_H
-
-#include <asm/cpuid/api.h>
-#include <asm/cpuid/types.h>
-
-/**
- * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
- * @regs:	Output parameter
- *
- * Query CPUID leaf 0x2 and store its output in @regs.	Force set any
- * invalid 1-byte descriptor returned by the hardware to zero (the NULL
- * cache/TLB descriptor) before returning it to the caller.
- *
- * Use for_each_leaf_0x2_entry() to iterate over the register output in
- * parsed form.
- */
-static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
-{
-	cpuid_leaf(0x2, regs);
-
-	/*
-	 * All Intel CPUs must report an iteration count of 1.	In case
-	 * of bogus hardware, treat all returned descriptors as NULL.
-	 */
-	if (regs->desc[0] != 0x01) {
-		for (int i = 0; i < 4; i++)
-			regs->regv[i] = 0;
-		return;
-	}
-
-	/*
-	 * The most significant bit (MSB) of each register must be clear.
-	 * If a register is invalid, replace its descriptors with NULL.
-	 */
-	for (int i = 0; i < 4; i++) {
-		if (regs->reg[i].invalid)
-			regs->regv[i] = 0;
-	}
-}
-
-/**
- * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
- * @regs:   Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
- * @__ptr:  u8 pointer, for macro internal use only
- * @entry:  Pointer to parsed descriptor information at each iteration
- *
- * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
- * @regs.  Provide the parsed information for each descriptor through @entry.
- *
- * To handle cache-specific descriptors, switch on @entry->c_type.  For TLB
- * descriptors, switch on @entry->t_type.
- *
- * Example usage for cache descriptors::
- *
- *	const struct leaf_0x2_table *entry;
- *	union leaf_0x2_regs regs;
- *	u8 *ptr;
- *
- *	cpuid_get_leaf_0x2_regs(&regs);
- *	for_each_leaf_0x2_entry(regs, ptr, entry) {
- *		switch (entry->c_type) {
- *			...
- *		}
- *	}
- */
-#define for_each_leaf_0x2_entry(regs, __ptr, entry)				\
-	for (__ptr = &(regs).desc[1];						\
-	     __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]);	\
-	     __ptr++)
-
-#endif /* _ASM_X86_CPUID_LEAF_0x2_API_H */
diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index c95fee66e148..8a00364b79de 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -31,8 +31,7 @@ enum cpuid_regs_idx {
 #define CPUID_LEAF_TILE		0x1d
 
 /*
- * Types for CPUID(0x2) parsing
- * Check <asm/cpuid/leaf_0x2_api.h>
+ * Types for CPUID(0x2) parsing:
  */
 
 struct leaf_0x2_reg {
-- 
2.49.0

[PATCH v1 2/9] x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header

[Ahmed S. Darwish]

The main CPUID header <asm/cpuid.h> was originally a storefront for the
headers:

    <asm/cpuid/api.h>
    <asm/cpuid/leaf_0x2_api.h>

Now that the latter CPUID(0x2) header has been merged into the former,
there is no practical difference between <asm/cpuid.h> and
<asm/cpuid/api.h>

Remove <asm/cpuid.h> and let all call-sites directly include
<asm/cpuid/api.h>.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/boot/compressed/sev.c        | 2 +-
 arch/x86/coco/sev/core.c              | 2 +-
 arch/x86/events/intel/pt.c            | 2 +-
 arch/x86/include/asm/cpuid.h          | 8 --------
 arch/x86/include/asm/processor.h      | 2 +-
 arch/x86/kernel/acpi/cstate.c         | 2 +-
 arch/x86/kernel/amd_nb.c              | 2 +-
 arch/x86/kernel/cpu/cacheinfo.c       | 2 +-
 arch/x86/kernel/cpu/common.c          | 2 +-
 arch/x86/kernel/cpu/intel.c           | 2 +-
 arch/x86/kernel/fpu/xstate.c          | 2 +-
 arch/x86/kernel/hpet.c                | 2 +-
 arch/x86/kernel/process.c             | 2 +-
 arch/x86/kernel/smpboot.c             | 2 +-
 arch/x86/kernel/tsc.c                 | 2 +-
 arch/x86/kvm/cpuid.c                  | 2 +-
 arch/x86/virt/svm/sev.c               | 2 +-
 arch/x86/xen/enlighten_pv.c           | 2 +-
 drivers/acpi/acpi_pad.c               | 2 +-
 drivers/dma/ioat/dca.c                | 2 +-
 drivers/idle/intel_idle.c             | 2 +-
 drivers/platform/x86/intel/pmc/core.c | 2 +-
 sound/soc/intel/avs/tgl.c             | 2 +-
 23 files changed, 22 insertions(+), 30 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid.h

diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index 0003e4416efd..f054bf52c10a 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -21,7 +21,7 @@
 #include <asm/fpu/xcr.h>
 #include <asm/ptrace.h>
 #include <asm/svm.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 
 #include "error.h"
 #include "../msr.h"
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index b0c1a7a57497..836fc4ce37d0 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -41,7 +41,7 @@
 #include <asm/smp.h>
 #include <asm/cpu.h>
 #include <asm/apic.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cmdline.h>
 
 #define DR7_RESET_VALUE        0x400
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index fa37565f6418..5ec16f31b904 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -18,7 +18,7 @@
 #include <linux/slab.h>
 #include <linux/device.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/perf_event.h>
 #include <asm/insn.h>
 #include <asm/io.h>
diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h
deleted file mode 100644
index d5749b25fa10..000000000000
--- a/arch/x86/include/asm/cpuid.h
+++ /dev/null
@@ -1,8 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-
-#ifndef _ASM_X86_CPUID_H
-#define _ASM_X86_CPUID_H
-
-#include <asm/cpuid/api.h>
-
-#endif /* _ASM_X86_CPUID_H */
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 5d2f7e5aff26..f639df061f09 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -16,7 +16,7 @@ struct vm86;
 #include <uapi/asm/sigcontext.h>
 #include <asm/current.h>
 #include <asm/cpufeatures.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/page.h>
 #include <asm/pgtable_types.h>
 #include <asm/percpu.h>
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index d5ac34186555..8698d66563ed 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -14,7 +14,7 @@
 
 #include <acpi/processor.h>
 #include <asm/cpu_device_id.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/mwait.h>
 #include <asm/special_insns.h>
 #include <asm/smp.h>
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index ffaad175cee2..cb4de00c36e7 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -15,7 +15,7 @@
 #include <linux/pci_ids.h>
 
 #include <asm/amd/nb.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 
 static u32 *flush_words;
 
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index f866d94352fb..6d61f7dff9e7 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -16,7 +16,7 @@
 #include <asm/amd/nb.h>
 #include <asm/cacheinfo.h>
 #include <asm/cpufeature.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/mtrr.h>
 #include <asm/smp.h>
 #include <asm/tlbflush.h>
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index e5734df3b4a1..9f0f6dcb2f7d 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -29,7 +29,7 @@
 
 #include <asm/alternative.h>
 #include <asm/cmdline.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/perf_event.h>
 #include <asm/mmu_context.h>
 #include <asm/doublefault.h>
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index a6493f60b3f2..ade5557dd3f8 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -16,7 +16,7 @@
 #include <asm/cpu_device_id.h>
 #include <asm/cpufeature.h>
 #include <asm/cpu.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/hwcap2.h>
 #include <asm/intel-family.h>
 #include <asm/microcode.h>
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 6a41d1610d8b..d67636806c8d 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -20,7 +20,7 @@
 #include <asm/fpu/signal.h>
 #include <asm/fpu/xcr.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/tlbflush.h>
 #include <asm/prctl.h>
 #include <asm/elf.h>
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index 7f4b2966e15c..e786664b735f 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -7,7 +7,7 @@
 #include <linux/cpu.h>
 #include <linux/irq.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/irq_remapping.h>
 #include <asm/hpet.h>
 #include <asm/time.h>
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 962c3ce39323..6e2f494472ae 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -30,7 +30,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/entry-common.h>
 #include <asm/cpu.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/apic.h>
 #include <linux/uaccess.h>
 #include <asm/mwait.h>
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index d6cf1e23c2a3..d7d61b3de2bf 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -64,7 +64,7 @@
 
 #include <asm/acpi.h>
 #include <asm/cacheinfo.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/desc.h>
 #include <asm/nmi.h>
 #include <asm/irq.h>
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 88e5a4ed9db3..56a1b7c5cf4e 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -16,7 +16,7 @@
 #include <linux/static_key.h>
 #include <linux/static_call.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/hpet.h>
 #include <asm/timer.h>
 #include <asm/vgtod.h>
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 571c906ffcbf..7f43d8d24fbe 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -21,7 +21,7 @@
 #include <asm/user.h>
 #include <asm/fpu/xstate.h>
 #include <asm/sgx.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include "cpuid.h"
 #include "lapic.h"
 #include "mmu.h"
diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c
index fc473ca12c44..10a78a98e2dd 100644
--- a/arch/x86/virt/svm/sev.c
+++ b/arch/x86/virt/svm/sev.c
@@ -27,7 +27,7 @@
 #include <asm/smp.h>
 #include <asm/cpu.h>
 #include <asm/apic.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cmdline.h>
 #include <asm/iommu.h>
 
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index 846b5737d320..21c7f524766e 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -49,7 +49,7 @@
 #include <xen/hvc-console.h>
 #include <xen/acpi.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/paravirt.h>
 #include <asm/apic.h>
 #include <asm/page.h>
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index 3fde4496f8a2..6f8bbe1247a5 100644
--- a/drivers/acpi/acpi_pad.c
+++ b/drivers/acpi/acpi_pad.c
@@ -19,7 +19,7 @@
 #include <linux/acpi.h>
 #include <linux/perf_event.h>
 #include <linux/platform_device.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/mwait.h>
 #include <xen/xen.h>
 
diff --git a/drivers/dma/ioat/dca.c b/drivers/dma/ioat/dca.c
index c9aba2304de7..5d3c0ae6b342 100644
--- a/drivers/dma/ioat/dca.c
+++ b/drivers/dma/ioat/dca.c
@@ -10,7 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/dca.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 
 /* either a kernel change is needed, or we need something like this in kernel */
 #ifndef CONFIG_SMP
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 976f5be54e36..d0b94dbc0835 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -51,7 +51,7 @@
 #include <linux/notifier.h>
 #include <linux/cpu.h>
 #include <linux/moduleparam.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cpu_device_id.h>
 #include <asm/intel-family.h>
 #include <asm/mwait.h>
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index 7a1d11f2914f..492c7b672bd7 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -22,7 +22,7 @@
 #include <linux/suspend.h>
 #include <linux/units.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cpu_device_id.h>
 #include <asm/intel-family.h>
 #include <asm/msr.h>
diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c
index 56905f2b9eb2..9dbb3ad0954a 100644
--- a/sound/soc/intel/avs/tgl.c
+++ b/sound/soc/intel/avs/tgl.c
@@ -47,7 +47,7 @@ static int avs_tgl_config_basefw(struct avs_dev *adev)
 #ifdef CONFIG_X86
 	unsigned int ecx;
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 	ecx = cpuid_ecx(CPUID_TSC_LEAF);
 	if (ecx) {
 		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(ecx), &ecx);
-- 
2.49.0

[PATCH v1 3/9] x86/cpuid: Rename have_cpuid_p() to cpuid_feature()

[Ahmed S. Darwish]

In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
namespace, rename have_cpuid_p() to cpuid_feature().

Adjust all call-sites accordingly.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/api.h     |  4 ++--
 arch/x86/kernel/cpu/common.c         | 10 +++++-----
 arch/x86/kernel/cpu/microcode/core.c |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index ff8891a0b6c8..c0211fcdc706 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -14,9 +14,9 @@
  */
 
 #ifdef CONFIG_X86_32
-bool have_cpuid_p(void);
+bool cpuid_feature(void);
 #else
-static inline bool have_cpuid_p(void)
+static inline bool cpuid_feature(void)
 {
 	return true;
 }
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 9f0f6dcb2f7d..def7af1dbd55 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -321,7 +321,7 @@ static int __init cachesize_setup(char *str)
 __setup("cachesize=", cachesize_setup);
 
 /* Probe for the CPUID instruction */
-bool have_cpuid_p(void)
+bool cpuid_feature(void)
 {
 	return flag_is_changeable_p(X86_EFLAGS_ID);
 }
@@ -1626,11 +1626,11 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 	memset(&c->x86_capability, 0, sizeof(c->x86_capability));
 	c->extended_cpuid_level = 0;
 
-	if (!have_cpuid_p())
+	if (!cpuid_feature())
 		identify_cpu_without_cpuid(c);
 
 	/* cyrix could have cpuid enabled via c_identify()*/
-	if (have_cpuid_p()) {
+	if (cpuid_feature()) {
 		cpu_detect(c);
 		get_cpu_vendor(c);
 		intel_unlock_cpuid_leafs(c);
@@ -1790,11 +1790,11 @@ static void generic_identify(struct cpuinfo_x86 *c)
 {
 	c->extended_cpuid_level = 0;
 
-	if (!have_cpuid_p())
+	if (!cpuid_feature())
 		identify_cpu_without_cpuid(c);
 
 	/* cyrix could have cpuid enabled via c_identify()*/
-	if (!have_cpuid_p())
+	if (!cpuid_feature())
 		return;
 
 	cpu_detect(c);
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index b3658d11e7b6..1395fa72960f 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -125,7 +125,7 @@ void __init load_ucode_bsp(void)
 	unsigned int cpuid_1_eax;
 	bool intel = true;
 
-	if (!have_cpuid_p())
+	if (!cpuid_feature())
 		return;
 
 	cpuid_1_eax = native_cpuid_eax(1);
-- 
2.49.0

[PATCH v1 4/9] x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()

[Ahmed S. Darwish]

In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
namespace, rename hypervisor_cpuid_base() to cpuid_hypervisor_base().

To align with the new style, also rename:

    for_each_possible_hypervisor_cpuid_base(function)

to:

    for_each_possible_cpuid_hypervisor_base(function)

Adjust all call-sites accordingly.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/acrn.h           | 2 +-
 arch/x86/include/asm/cpuid/api.h      | 6 +++---
 arch/x86/include/asm/xen/hypervisor.h | 2 +-
 arch/x86/kernel/jailhouse.c           | 2 +-
 arch/x86/kernel/kvm.c                 | 2 +-
 arch/x86/kvm/cpuid.c                  | 2 +-
 6 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/acrn.h b/arch/x86/include/asm/acrn.h
index 1dd14381bcb6..b509c622e6f4 100644
--- a/arch/x86/include/asm/acrn.h
+++ b/arch/x86/include/asm/acrn.h
@@ -25,7 +25,7 @@ void acrn_remove_intr_handler(void);
 static inline u32 acrn_cpuid_base(void)
 {
 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
-		return hypervisor_cpuid_base("ACRNACRNACRN", 0);
+		return cpuid_hypervisor_base("ACRNACRNACRN", 0);
 
 	return 0;
 }
diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index c0211fcdc706..0e4b53306e99 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -188,14 +188,14 @@ static __always_inline bool cpuid_function_is_indexed(u32 function)
 	return false;
 }
 
-#define for_each_possible_hypervisor_cpuid_base(function) \
+#define for_each_possible_cpuid_hypervisor_base(function) \
 	for (function = 0x40000000; function < 0x40010000; function += 0x100)
 
-static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves)
+static inline u32 cpuid_hypervisor_base(const char *sig, u32 leaves)
 {
 	u32 base, eax, signature[3];
 
-	for_each_possible_hypervisor_cpuid_base(base) {
+	for_each_possible_cpuid_hypervisor_base(base) {
 		cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
 
 		/*
diff --git a/arch/x86/include/asm/xen/hypervisor.h b/arch/x86/include/asm/xen/hypervisor.h
index bd0fc69a10a7..09b15a0e2d2e 100644
--- a/arch/x86/include/asm/xen/hypervisor.h
+++ b/arch/x86/include/asm/xen/hypervisor.h
@@ -43,7 +43,7 @@ extern struct start_info *xen_start_info;
 
 static inline uint32_t xen_cpuid_base(void)
 {
-	return hypervisor_cpuid_base(XEN_SIGNATURE, 2);
+	return cpuid_hypervisor_base(XEN_SIGNATURE, 2);
 }
 
 struct pci_dev;
diff --git a/arch/x86/kernel/jailhouse.c b/arch/x86/kernel/jailhouse.c
index cd8ed1edbf9e..07da72de80ba 100644
--- a/arch/x86/kernel/jailhouse.c
+++ b/arch/x86/kernel/jailhouse.c
@@ -49,7 +49,7 @@ static uint32_t jailhouse_cpuid_base(void)
 	    !boot_cpu_has(X86_FEATURE_HYPERVISOR))
 		return 0;
 
-	return hypervisor_cpuid_base("Jailhouse\0\0\0", 0);
+	return cpuid_hypervisor_base("Jailhouse\0\0\0", 0);
 }
 
 static uint32_t __init jailhouse_detect(void)
diff --git a/arch/x86/kernel/kvm.c b/arch/x86/kernel/kvm.c
index 3be9b3342c67..35d3d2803c57 100644
--- a/arch/x86/kernel/kvm.c
+++ b/arch/x86/kernel/kvm.c
@@ -874,7 +874,7 @@ static noinline uint32_t __kvm_cpuid_base(void)
 		return 0;	/* So we don't blow up on old processors */
 
 	if (boot_cpu_has(X86_FEATURE_HYPERVISOR))
-		return hypervisor_cpuid_base(KVM_SIGNATURE, 0);
+		return cpuid_hypervisor_base(KVM_SIGNATURE, 0);
 
 	return 0;
 }
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 7f43d8d24fbe..d153719302a2 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -236,7 +236,7 @@ static struct kvm_hypervisor_cpuid kvm_get_hypervisor_cpuid(struct kvm_vcpu *vcp
 	struct kvm_cpuid_entry2 *entry;
 	u32 base;
 
-	for_each_possible_hypervisor_cpuid_base(base) {
+	for_each_possible_cpuid_hypervisor_base(base) {
 		entry = kvm_find_cpuid_entry(vcpu, base);
 
 		if (entry) {
-- 
2.49.0

[PATCH v1 5/9] x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()

[Ahmed S. Darwish]

Rename the CPUID(0x2) register accessor function:

    cpuid_get_leaf_0x2_regs(regs)

to:

    cpuid_leaf_0x2(regs)

for consistency with other <cpuid/api.h> accessors that return full CPUID
registers outputs like:

    cpuid_leaf(regs)
    cpuid_subleaf(regs)

In the same vein, rename the CPUID(0x2) iteration macro:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

to include "cpuid" in the macro name, and since what is iterated upon is
CPUID(0x2) cache and TLB "descriptos", not "entries".  Prefix an
underscore to that iterator macro parameters, so that the newly renamed
'desc' parameter do not get mixed with "union leaf_0x2_regs :: desc[]" in
the macro's implementation.

Adjust all the affected call-sites accordingly.

While at it, use "CPUID(0x2)" instead of "CPUID leaf 0x2" as this is the
recommended style.

References: 62e565273993 ("x86/cacheinfo: Standardize header files and CPUID references")
References: 718f9038acc5 ("x86/cpuid: Remove obsolete CPUID(0x2) iteration macro")
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/include/asm/cpuid/api.h | 34 ++++++++++++++++----------------
 arch/x86/kernel/cpu/cacheinfo.c  |  4 ++--
 arch/x86/kernel/cpu/intel.c      |  4 ++--
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 0e4b53306e99..e957f09d8a8f 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -216,17 +216,17 @@ static inline u32 cpuid_hypervisor_base(const char *sig, u32 leaves)
  */
 
 /**
- * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
+ * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output
  * @regs:	Output parameter
  *
- * Query CPUID leaf 0x2 and store its output in @regs.	Force set any
+ * Query CPUID(0x2) and store its output in @regs.  Force set any
  * invalid 1-byte descriptor returned by the hardware to zero (the NULL
  * cache/TLB descriptor) before returning it to the caller.
  *
- * Use for_each_leaf_0x2_entry() to iterate over the register output in
+ * Use for_each_cpuid_0x2_desc() to iterate over the register output in
  * parsed form.
  */
-static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
+static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs)
 {
 	cpuid_leaf(0x2, regs);
 
@@ -251,34 +251,34 @@ static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
 }
 
 /**
- * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
- * @regs:   Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
+ * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
+ * @regs:   CPUID(0x2) register output, as returned by cpuid_leaf_0x2()
  * @__ptr:  u8 pointer, for macro internal use only
- * @entry:  Pointer to parsed descriptor information at each iteration
+ * @desc:   Pointer to parsed CPUID(0x2) descriptor at each iteration
  *
- * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
- * @regs.  Provide the parsed information for each descriptor through @entry.
+ * Loop over the 1-byte descriptors in the passed CPUID(0x2) output registers
+ * @regs.  Provide the parsed information for each descriptor through @desc.
  *
  * To handle cache-specific descriptors, switch on @entry->c_type.  For TLB
  * descriptors, switch on @entry->t_type.
  *
  * Example usage for cache descriptors::
  *
- *	const struct leaf_0x2_table *entry;
+ *	const struct leaf_0x2_table *desc;
  *	union leaf_0x2_regs regs;
  *	u8 *ptr;
  *
- *	cpuid_get_leaf_0x2_regs(&regs);
- *	for_each_leaf_0x2_entry(regs, ptr, entry) {
- *		switch (entry->c_type) {
+ *	cpuid_leaf_0x2(&regs);
+ *	for_each_cpuid_0x2_desc(regs, ptr, desc) {
+ *		switch (desc->c_type) {
  *			...
  *		}
  *	}
  */
-#define for_each_leaf_0x2_entry(regs, __ptr, entry)				\
-	for (__ptr = &(regs).desc[1];						\
-	     __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]);	\
-	     __ptr++)
+#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc)				\
+	for (_ptr = &(_regs).desc[1];						\
+	     _ptr < &(_regs).desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);	\
+	     _ptr++)
 
 /*
  * CPUID(0x80000006) parsing:
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 6d61f7dff9e7..b6349c1792dd 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -388,8 +388,8 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 	if (c->cpuid_level < 2)
 		return;
 
-	cpuid_get_leaf_0x2_regs(&regs);
-	for_each_leaf_0x2_entry(regs, ptr, entry) {
+	cpuid_leaf_0x2(&regs);
+	for_each_cpuid_0x2_desc(regs, ptr, entry) {
 		switch (entry->c_type) {
 		case CACHE_L1_INST:	l1i += entry->c_size; break;
 		case CACHE_L1_DATA:	l1d += entry->c_size; break;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index ade5557dd3f8..d4efca7e4bd6 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -716,8 +716,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 	if (c->cpuid_level < 2)
 		return;
 
-	cpuid_get_leaf_0x2_regs(&regs);
-	for_each_leaf_0x2_entry(regs, ptr, entry)
+	cpuid_leaf_0x2(&regs);
+	for_each_cpuid_0x2_desc(regs, ptr, entry)
 		intel_tlb_lookup(entry);
 }
 
-- 
2.49.0

[PATCH v1 6/9] x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter

[Ahmed S. Darwish]

The CPUID(0x2) descriptors iterator has been renamed from:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

since it iterates over CPUID(0x2) cache and TLB "descriptors", not
"entries".

In the macro's x86/cacheinfo call-site, rename the parameter denoting the
parsed descriptor at each iteration from 'entry' to 'desc'.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/cacheinfo.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index b6349c1792dd..adfa7e8bb865 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -381,7 +381,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3,
 static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 {
 	unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0;
-	const struct leaf_0x2_table *entry;
+	const struct leaf_0x2_table *desc;
 	union leaf_0x2_regs regs;
 	u8 *ptr;
 
@@ -389,12 +389,12 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 		return;
 
 	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, entry) {
-		switch (entry->c_type) {
-		case CACHE_L1_INST:	l1i += entry->c_size; break;
-		case CACHE_L1_DATA:	l1d += entry->c_size; break;
-		case CACHE_L2:		l2  += entry->c_size; break;
-		case CACHE_L3:		l3  += entry->c_size; break;
+	for_each_cpuid_0x2_desc(regs, ptr, desc) {
+		switch (desc->c_type) {
+		case CACHE_L1_INST:	l1i += desc->c_size; break;
+		case CACHE_L1_DATA:	l1d += desc->c_size; break;
+		case CACHE_L2:		l2  += desc->c_size; break;
+		case CACHE_L3:		l3  += desc->c_size; break;
 		}
 	}
 
-- 
2.49.0

[PATCH v1 7/9] x86/cpu: Rename CPUID(0x2) descriptors iterator parameter

[Ahmed S. Darwish]

The CPUID(0x2) descriptors iterator has been renamed from:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

since it iterates over CPUID(0x2) cache and TLB "descriptors", not
"entries".

In the macro's x86/cpu call-site, rename the parameter denoting the
parsed descriptor at each iteration from 'entry' to 'desc'.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/kernel/cpu/intel.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index d4efca7e4bd6..cfcf9b3d270f 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -648,11 +648,11 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 }
 #endif
 
-static void intel_tlb_lookup(const struct leaf_0x2_table *entry)
+static void intel_tlb_lookup(const struct leaf_0x2_table *desc)
 {
-	short entries = entry->entries;
+	short entries = desc->entries;
 
-	switch (entry->t_type) {
+	switch (desc->t_type) {
 	case STLB_4K:
 		tlb_lli_4k = max(tlb_lli_4k, entries);
 		tlb_lld_4k = max(tlb_lld_4k, entries);
@@ -709,7 +709,7 @@ static void intel_tlb_lookup(const struct leaf_0x2_table *entry)
 
 static void intel_detect_tlb(struct cpuinfo_x86 *c)
 {
-	const struct leaf_0x2_table *entry;
+	const struct leaf_0x2_table *desc;
 	union leaf_0x2_regs regs;
 	u8 *ptr;
 
@@ -717,8 +717,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 		return;
 
 	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, entry)
-		intel_tlb_lookup(entry);
+	for_each_cpuid_0x2_desc(regs, ptr, desc)
+		intel_tlb_lookup(desc);
 }
 
 static const struct cpu_dev intel_cpu_dev = {
-- 
2.49.0

[PATCH v1 8/9] x86/cpuid: Rename native_cpuid() to cpuid_native()

[Ahmed S. Darwish]

In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
namespace, rename native_cpuid() to cpuid_native().

Adjust all call-sites accordingly.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/boot/compressed/sev.c           | 6 +++---
 arch/x86/include/asm/cpuid/api.h         | 6 +++---
 arch/x86/kernel/cpu/microcode/intel.c    | 2 +-
 arch/x86/kernel/cpu/microcode/internal.h | 4 ++--
 arch/x86/kernel/paravirt.c               | 2 +-
 arch/x86/mm/mem_encrypt_identity.c       | 6 +++---
 arch/x86/xen/enlighten_pv.c              | 4 ++--
 7 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index f054bf52c10a..4b617f8f9b7f 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -494,7 +494,7 @@ static int sev_check_cpu_support(void)
 	/* Check for the SME/SEV support leaf */
 	eax = 0x80000000;
 	ecx = 0;
-	native_cpuid(&eax, &ebx, &ecx, &edx);
+	cpuid_native(&eax, &ebx, &ecx, &edx);
 	if (eax < 0x8000001f)
 		return -ENODEV;
 
@@ -508,7 +508,7 @@ static int sev_check_cpu_support(void)
 	 */
 	eax = 0x8000001f;
 	ecx = 0;
-	native_cpuid(&eax, &ebx, &ecx, &edx);
+	cpuid_native(&eax, &ebx, &ecx, &edx);
 	/* Check whether SEV is supported */
 	if (!(eax & BIT(1)))
 		return -ENODEV;
@@ -666,7 +666,7 @@ bool early_is_sevsnp_guest(void)
 		 */
 		eax = 0x8000001f;
 		ecx = 0;
-		native_cpuid(&eax, &ebx, &ecx, &edx);
+		cpuid_native(&eax, &ebx, &ecx, &edx);
 		if (eax & BIT(28)) {
 			struct msr m;
 
diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index e957f09d8a8f..7f4644747649 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -22,7 +22,7 @@ static inline bool cpuid_feature(void)
 }
 #endif
 
-static inline void native_cpuid(u32 *eax, u32 *ebx,
+static inline void cpuid_native(u32 *eax, u32 *ebx,
 				u32 *ecx, u32 *edx)
 {
 	/* ecx is often an input as well as an output. */
@@ -40,7 +40,7 @@ static inline u32 native_cpuid_##reg(u32 op)			\
 {								\
 	u32 eax = op, ebx, ecx = 0, edx;			\
 								\
-	native_cpuid(&eax, &ebx, &ecx, &edx);			\
+	cpuid_native(&eax, &ebx, &ecx, &edx);			\
 								\
 	return reg;						\
 }
@@ -56,7 +56,7 @@ NATIVE_CPUID_REG(edx)
 #ifdef CONFIG_PARAVIRT_XXL
 # include <asm/paravirt.h>
 #else
-# define __cpuid native_cpuid
+# define __cpuid	cpuid_native
 #endif
 
 /*
diff --git a/arch/x86/kernel/cpu/microcode/intel.c b/arch/x86/kernel/cpu/microcode/intel.c
index 819199bc0119..66693831f665 100644
--- a/arch/x86/kernel/cpu/microcode/intel.c
+++ b/arch/x86/kernel/cpu/microcode/intel.c
@@ -347,7 +347,7 @@ static __init bool load_builtin_intel_microcode(struct cpio_data *cp)
 	if (IS_ENABLED(CONFIG_X86_32))
 		return false;
 
-	native_cpuid(&eax, &ebx, &ecx, &edx);
+	cpuid_native(&eax, &ebx, &ecx, &edx);
 
 	sprintf(name, "intel-ucode/%02x-%02x-%02x",
 		x86_family(eax), x86_model(eax), x86_stepping(eax));
diff --git a/arch/x86/kernel/cpu/microcode/internal.h b/arch/x86/kernel/cpu/microcode/internal.h
index 5df621752fef..6049fd7ac16a 100644
--- a/arch/x86/kernel/cpu/microcode/internal.h
+++ b/arch/x86/kernel/cpu/microcode/internal.h
@@ -73,7 +73,7 @@ static inline int x86_cpuid_vendor(void)
 	u32 eax = 0x00000000;
 	u32 ebx, ecx = 0, edx;
 
-	native_cpuid(&eax, &ebx, &ecx, &edx);
+	cpuid_native(&eax, &ebx, &ecx, &edx);
 
 	if (CPUID_IS(CPUID_INTEL1, CPUID_INTEL2, CPUID_INTEL3, ebx, ecx, edx))
 		return X86_VENDOR_INTEL;
@@ -89,7 +89,7 @@ static inline unsigned int x86_cpuid_family(void)
 	u32 eax = 0x00000001;
 	u32 ebx, ecx = 0, edx;
 
-	native_cpuid(&eax, &ebx, &ecx, &edx);
+	cpuid_native(&eax, &ebx, &ecx, &edx);
 
 	return x86_family(eax);
 }
diff --git a/arch/x86/kernel/paravirt.c b/arch/x86/kernel/paravirt.c
index 1ccd05d8999f..e2c812beb06c 100644
--- a/arch/x86/kernel/paravirt.c
+++ b/arch/x86/kernel/paravirt.c
@@ -122,7 +122,7 @@ struct paravirt_patch_template pv_ops = {
 	.cpu.io_delay		= native_io_delay,
 
 #ifdef CONFIG_PARAVIRT_XXL
-	.cpu.cpuid		= native_cpuid,
+	.cpu.cpuid		= cpuid_native,
 	.cpu.get_debugreg	= pv_native_get_debugreg,
 	.cpu.set_debugreg	= pv_native_set_debugreg,
 	.cpu.read_cr0		= native_read_cr0,
diff --git a/arch/x86/mm/mem_encrypt_identity.c b/arch/x86/mm/mem_encrypt_identity.c
index 5eecdd92da10..6bad28dd8b07 100644
--- a/arch/x86/mm/mem_encrypt_identity.c
+++ b/arch/x86/mm/mem_encrypt_identity.c
@@ -501,7 +501,7 @@ void __head sme_enable(struct boot_params *bp)
 	/* Check for the SME/SEV support leaf */
 	eax = 0x80000000;
 	ecx = 0;
-	native_cpuid(&eax, &ebx, &ecx, &edx);
+	cpuid_native(&eax, &ebx, &ecx, &edx);
 	if (eax < 0x8000001f)
 		return;
 
@@ -518,7 +518,7 @@ void __head sme_enable(struct boot_params *bp)
 	 */
 	eax = 0x8000001f;
 	ecx = 0;
-	native_cpuid(&eax, &ebx, &ecx, &edx);
+	cpuid_native(&eax, &ebx, &ecx, &edx);
 	/* Check whether SEV or SME is supported */
 	if (!(eax & (AMD_SEV_BIT | AMD_SME_BIT)))
 		return;
@@ -552,7 +552,7 @@ void __head sme_enable(struct boot_params *bp)
 		 */
 		eax = 1;
 		ecx = 0;
-		native_cpuid(&eax, &ebx, &ecx, &edx);
+		cpuid_native(&eax, &ebx, &ecx, &edx);
 		if (ecx & BIT(31))
 			return;
 
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index 21c7f524766e..d1a1a3546bd5 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -327,7 +327,7 @@ static bool __init xen_check_mwait(void)
 	ax = 1;
 	cx = 0;
 
-	native_cpuid(&ax, &bx, &cx, &dx);
+	cpuid_native(&ax, &bx, &cx, &dx);
 
 	mwait_mask = (1 << (X86_FEATURE_EST % 32)) |
 		     (1 << (X86_FEATURE_MWAIT % 32));
@@ -344,7 +344,7 @@ static bool __init xen_check_mwait(void)
 	cx = 0;
 	dx = 0;
 
-	native_cpuid(&ax, &bx, &cx, &dx);
+	cpuid_native(&ax, &bx, &cx, &dx);
 
 	/* Ask the Hypervisor whether to clear ACPI_PROC_CAP_C_C2C3_FFH. If so,
 	 * don't expose MWAIT_LEAF and let ACPI pick the IOPORT version of C3.
-- 
2.49.0

[PATCH v1 9/9] x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()

[Ahmed S. Darwish]

In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
namespace, rename native_cpuid_REG() to cpuid_native_REG().

To beetter align with the new namespace, also rename the internal
NATIVE_CPUID_REG() macro to __CPUID_NATIVE_REG().

Adjust all call-sites accordingly.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
---
 arch/x86/boot/compressed/pgtable_64.c   |  4 ++--
 arch/x86/include/asm/cpuid/api.h        | 12 ++++++------
 arch/x86/include/asm/microcode.h        |  2 +-
 arch/x86/kernel/cpu/microcode/amd.c     |  2 +-
 arch/x86/kernel/cpu/microcode/core.c    |  6 +++---
 arch/x86/kernel/head32.c                |  2 +-
 drivers/firmware/efi/libstub/x86-5lvl.c |  4 ++--
 7 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/arch/x86/boot/compressed/pgtable_64.c b/arch/x86/boot/compressed/pgtable_64.c
index d8c5de40669d..8cfe50988aa2 100644
--- a/arch/x86/boot/compressed/pgtable_64.c
+++ b/arch/x86/boot/compressed/pgtable_64.c
@@ -125,8 +125,8 @@ asmlinkage void configure_5level_paging(struct boot_params *bp, void *pgtable)
 	 */
 	if (IS_ENABLED(CONFIG_X86_5LEVEL) &&
 			!cmdline_find_option_bool("no5lvl") &&
-			native_cpuid_eax(0) >= 7 &&
-			(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
+			cpuid_native_eax(0) >= 7 &&
+			(cpuid_native_ecx(7) & (1 << (X86_FEATURE_LA57 & 31)))) {
 		l5_required = true;
 
 		/* Initialize variables for 5-level paging */
diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index 7f4644747649..9f8a1176ad86 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -35,8 +35,8 @@ static inline void cpuid_native(u32 *eax, u32 *ebx,
 	    : "memory");
 }
 
-#define NATIVE_CPUID_REG(reg)					\
-static inline u32 native_cpuid_##reg(u32 op)			\
+#define __CPUID_NATIVE_REG(reg)					\
+static inline u32 cpuid_native_##reg(u32 op)			\
 {								\
 	u32 eax = op, ebx, ecx = 0, edx;			\
 								\
@@ -48,10 +48,10 @@ static inline u32 native_cpuid_##reg(u32 op)			\
 /*
  * Native CPUID functions returning a single datum:
  */
-NATIVE_CPUID_REG(eax)
-NATIVE_CPUID_REG(ebx)
-NATIVE_CPUID_REG(ecx)
-NATIVE_CPUID_REG(edx)
+__CPUID_NATIVE_REG(eax)
+__CPUID_NATIVE_REG(ebx)
+__CPUID_NATIVE_REG(ecx)
+__CPUID_NATIVE_REG(edx)
 
 #ifdef CONFIG_PARAVIRT_XXL
 # include <asm/paravirt.h>
diff --git a/arch/x86/include/asm/microcode.h b/arch/x86/include/asm/microcode.h
index 695e569159c1..755c9f693118 100644
--- a/arch/x86/include/asm/microcode.h
+++ b/arch/x86/include/asm/microcode.h
@@ -64,7 +64,7 @@ static inline u32 intel_get_microcode_revision(void)
 	native_wrmsrl(MSR_IA32_UCODE_REV, 0);
 
 	/* As documented in the SDM: Do a CPUID 1 here */
-	native_cpuid_eax(1);
+	cpuid_native_eax(1);
 
 	/* get the current revision from MSR 0x8B */
 	native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
diff --git a/arch/x86/kernel/cpu/microcode/amd.c b/arch/x86/kernel/cpu/microcode/amd.c
index 4a10d35e70aa..d757383b653c 100644
--- a/arch/x86/kernel/cpu/microcode/amd.c
+++ b/arch/x86/kernel/cpu/microcode/amd.c
@@ -1098,7 +1098,7 @@ static enum ucode_state load_microcode_amd(u8 family, const u8 *data, size_t siz
 
 static int __init save_microcode_in_initrd(void)
 {
-	unsigned int cpuid_1_eax = native_cpuid_eax(1);
+	unsigned int cpuid_1_eax = cpuid_native_eax(1);
 	struct cpuinfo_x86 *c = &boot_cpu_data;
 	struct cont_desc desc = { 0 };
 	enum ucode_state ret;
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index 1395fa72960f..9924b8238492 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -106,7 +106,7 @@ static bool __init check_loader_disabled_bsp(void)
 	 * completely accurate as xen pv guests don't see that CPUID bit set but
 	 * that's good enough as they don't land on the BSP path anyway.
 	 */
-	if (native_cpuid_ecx(1) & BIT(31))
+	if (cpuid_native_ecx(1) & BIT(31))
 		return true;
 
 	if (x86_cpuid_vendor() == X86_VENDOR_AMD) {
@@ -128,7 +128,7 @@ void __init load_ucode_bsp(void)
 	if (!cpuid_feature())
 		return;
 
-	cpuid_1_eax = native_cpuid_eax(1);
+	cpuid_1_eax = cpuid_native_eax(1);
 
 	switch (x86_cpuid_vendor()) {
 	case X86_VENDOR_INTEL:
@@ -162,7 +162,7 @@ void load_ucode_ap(void)
 	if (dis_ucode_ldr)
 		return;
 
-	cpuid_1_eax = native_cpuid_eax(1);
+	cpuid_1_eax = cpuid_native_eax(1);
 
 	switch (x86_cpuid_vendor()) {
 	case X86_VENDOR_INTEL:
diff --git a/arch/x86/kernel/head32.c b/arch/x86/kernel/head32.c
index de001b2146ab..43aa1cfc1b65 100644
--- a/arch/x86/kernel/head32.c
+++ b/arch/x86/kernel/head32.c
@@ -146,7 +146,7 @@ void __init __no_stack_protector mk_early_pgtbl_32(void)
 
 #ifdef CONFIG_MICROCODE_INITRD32
 	/* Running on a hypervisor? */
-	if (native_cpuid_ecx(1) & BIT(31))
+	if (cpuid_native_ecx(1) & BIT(31))
 		return;
 
 	params = (struct boot_params *)__pa_nodebug(&boot_params);
diff --git a/drivers/firmware/efi/libstub/x86-5lvl.c b/drivers/firmware/efi/libstub/x86-5lvl.c
index 77359e802181..db347c91edb3 100644
--- a/drivers/firmware/efi/libstub/x86-5lvl.c
+++ b/drivers/firmware/efi/libstub/x86-5lvl.c
@@ -34,8 +34,8 @@ efi_status_t efi_setup_5level_paging(void)
 		return EFI_SUCCESS;
 
 	/* check for 5 level paging support */
-	if (native_cpuid_eax(0) < 7 ||
-	    !(native_cpuid_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
+	if (cpuid_native_eax(0) < 7 ||
+	    !(cpuid_native_ecx(7) & (1 << (X86_FEATURE_LA57 & 31))))
 		return EFI_SUCCESS;
 
 	/* allocate some 32-bit addressable memory for code and a page table */
-- 
2.49.0

Re: [PATCH v1 0/9] x86/cpuid: Headers cleanup

[Ahmed S. Darwish]

On Thu, 08 May, Ahmed S. Darwish wrote:
>
> Simplify it into:
>
>     include/asm/
>     ├── api.h
>     └── types.h
>

Typo:

      include/asm/cpuid/
      ├── api.h
      └── types.h

Thanks,
Ahmed

Re: [PATCH v1 9/9] x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()

[Ahmed S. Darwish (dev)]

On Thu, 08 May 2025, Ahmed S. Darwish wrote:
>
> -	native_cpuid_eax(1);
> +	cpuid_native_eax(1);
>
...
>
> -	cpuid_1_eax = native_cpuid_eax(1);
> +	cpuid_1_eax = cpuid_native_eax(1);
>

Now that I'm looking at this with fresher eyes, I think below form would
be much better:

    cpuid_eax_native()
    cpuid_ebx_native()
    cpuid_ecx_native()
    cpuid_edx_native()

So that it aligns with:

    cpuid_eax()
    cpuid_ebx()
    cpuid_ecx()
    cpuid_edx()

at the rest of the <cpuid/api.h> header.  Thus the diff becomes:

-   cpuid_1_eax = native_cpuid_eax(1);
+   cpuid_1_eax = cpuid_eax_native(1);

-   if (native_cpuid_ecx(1) & BIT(31))
+   if (cpuid_ecx_native(1) & BIT(31))

But I'll wait for review feedback before rolling a v2.  Maybe people want
to keep having "native_" at the start, instead of forcing a strict
"cpuid_" namespace.

(With "CPUID refactoring" hat on, and as the above mini diff shows, I
 honestly think forcing a "cpuid_" namespace, even on native OPs, is much
 cleaner.)

Thanks,
~ Ahmed

Re: [PATCH v1 2/9] x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header

[Ingo Molnar]

* Ahmed S. Darwish <darwi@linutronix.de> wrote:

> The main CPUID header <asm/cpuid.h> was originally a storefront for the
> headers:
> 
>     <asm/cpuid/api.h>
>     <asm/cpuid/leaf_0x2_api.h>
> 
> Now that the latter CPUID(0x2) header has been merged into the former,
> there is no practical difference between <asm/cpuid.h> and
> <asm/cpuid/api.h>
> 
> Remove <asm/cpuid.h> and let all call-sites directly include
> <asm/cpuid/api.h>.
> 
> Suggested-by: Ingo Molnar <mingo@kernel.org>
> Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>

> diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h
> deleted file mode 100644
> index d5749b25fa10..000000000000
> --- a/arch/x86/include/asm/cpuid.h
> +++ /dev/null
> @@ -1,8 +0,0 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -
> -#ifndef _ASM_X86_CPUID_H
> -#define _ASM_X86_CPUID_H
> -
> -#include <asm/cpuid/api.h>
> -
> -#endif /* _ASM_X86_CPUID_H */

Note that in the tip:x86/core commit I've applied today I've delayed 
this removal of <asm/cpuid.h>, in case there's something in -next that 
started using it. I've adjusted the changelog accordingly.

We can remove it later on, shortly after -rc1 or so.

Thanks,

	Ingo

Re: [PATCH v1 4/9] x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()

[Ingo Molnar]

* Ahmed S. Darwish <darwi@linutronix.de> wrote:

> In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
> namespace, rename hypervisor_cpuid_base() to cpuid_hypervisor_base().
> 
> To align with the new style, also rename:
> 
>     for_each_possible_hypervisor_cpuid_base(function)
> 
> to:
> 
>     for_each_possible_cpuid_hypervisor_base(function)
> 
> Adjust all call-sites accordingly.
> 
> Suggested-by: Ingo Molnar <mingo@kernel.org>
> Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
> ---
>  arch/x86/include/asm/acrn.h           | 2 +-
>  arch/x86/include/asm/cpuid/api.h      | 6 +++---
>  arch/x86/include/asm/xen/hypervisor.h | 2 +-
>  arch/x86/kernel/jailhouse.c           | 2 +-
>  arch/x86/kernel/kvm.c                 | 2 +-
>  arch/x86/kvm/cpuid.c                  | 2 +-
>  6 files changed, 8 insertions(+), 8 deletions(-)

> -#define for_each_possible_hypervisor_cpuid_base(function) \
> +#define for_each_possible_cpuid_hypervisor_base(function) \
>  	for (function = 0x40000000; function < 0x40010000; function += 0x100)


> --- a/arch/x86/include/asm/xen/hypervisor.h
> +++ b/arch/x86/include/asm/xen/hypervisor.h
> @@ -43,7 +43,7 @@ extern struct start_info *xen_start_info;
>  
>  static inline uint32_t xen_cpuid_base(void)
>  {
> -	return hypervisor_cpuid_base(XEN_SIGNATURE, 2);
> +	return cpuid_hypervisor_base(XEN_SIGNATURE, 2);
>  }

So the interaction here looks a bit weird IMO (what is a 'hypervisor 
base'?), and I think the 'CPUID base' phrase should be immutable.

Ie. I think it would be more natural to call this method 
cpuid_base_hypervisor(), which would mix reasonably well with:

	kvm_cpuid_base()
	xen_cpuid_base()
	jailhouse_cpuid_base()

These lower level methods are prefixed with kvm_/xen_/jailhouse_, as 
most of their internal methods are.

Likewise, for_each_possible_cpuid_base_hypervisor()?

Thanks,

	Ingo

Re: [PATCH v1 0/9] x86/cpuid: Headers cleanup

[Ingo Molnar]

* Ahmed S. Darwish <darwi@linutronix.de> wrote:

> Hi,
> 
> This is a CPUID headers cleanup series, on top of tip:x86/cpu.  It is a
> precursor for the upcoming v2 of the CPUID parser:
> 
>     [PATCH v1 00/26] x86: Introduce centralized CPUID model
>     https://lore.kernel.org/lkml/20250506050437.10264-1-darwi@linutronix.de
> 
> as suggested by Ingo here:
> 
>     https://lore.kernel.org/lkml/aBnSgu_JyEi8fvog@gmail.com
> 
> * Summary:
> 
> The current CPUID header structure is:
> 
>     include/asm/
>     ├── cpuid
>     │   ├── api.h
>     │   ├── leaf_0x2_api.h
>     │   └── types.h
>     └── cpuid.h
> 
> Simplify it into:
> 
>     include/asm/
>     ├── api.h
>     └── types.h
> 
> Standardize the CPUID header namespace by enforcing a "cpuid_" prefix for
> all exported symbols.  That is:
> 
>     have_cpuid_p()		➤	cpuid_feature()
>     hypervisor_cpuid_base()	➤	cpuid_hypervisor_base()
>     native_cpuid()		➤	cpuid_native()
>     native_cpuid_REG()		➤	cpuid_native_REG()
> 
> Also rename:
> 
>     cpuid_get_leaf_0x2_regs()	➤	cpuid_leaf_0x2()
> 
> for consistency with the other <asm/cpuid/api.h> accessors that return
> full CPUID register output; i.e., cpuid_leaf() and cpuid_subleaf().
> 
> Finally, rename:
> 
>     for_each_leaf_0x2_entry()   ➤	for_each_cpuid_0x2_desc()
> 
> to include "cpuid" in the iterator name, and since what is being iterated
> upon is CPUID(0x2) cache and TLB "descriptos", not "entries".
> 
> * Testing:
> 
> - Basic one-by-one allyesconfig compilation
> 
> - Comparison of a before/after of below files:
> 
>   - /proc/cpuinfo
>   - /sys/devices/system/cpu/
>   - /sys/kernel/debug/x86/topo/
>   - dmesg --notime | grep 'Last level [id]TLB entries'
> 
> Thanks!
> 
> 8<--
> 
> Ahmed S. Darwish (9):
>   x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>
>   x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header
>   x86/cpuid: Rename have_cpuid_p() to cpuid_feature()
>   x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()
>   x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()
>   x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter
>   x86/cpu: Rename CPUID(0x2) descriptors iterator parameter
>   x86/cpuid: Rename native_cpuid() to cpuid_native()
>   x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()

Thank you for doing this. I've reviewed the series and applied these:

    x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>
    x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header
    x86/cpuid: Rename have_cpuid_p() to cpuid_feature()
    x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()
    x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter
    x86/cpu/intel: Rename CPUID(0x2) descriptors iterator parameter

I had some questions about:

    x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()
    x86/cpuid: Rename native_cpuid() to cpuid_native()

and you had better ideas about:

    x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()

Thanks,

	Ingo

Re: [PATCH v1 8/9] x86/cpuid: Rename native_cpuid() to cpuid_native()

[Ingo Molnar]

* Ahmed S. Darwish <darwi@linutronix.de> wrote:

> In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
> namespace, rename native_cpuid() to cpuid_native().
> 
> Adjust all call-sites accordingly.
> 
> Suggested-by: Ingo Molnar <mingo@kernel.org>
> Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
> ---
>  arch/x86/boot/compressed/sev.c           | 6 +++---
>  arch/x86/include/asm/cpuid/api.h         | 6 +++---
>  arch/x86/kernel/cpu/microcode/intel.c    | 2 +-
>  arch/x86/kernel/cpu/microcode/internal.h | 4 ++--
>  arch/x86/kernel/paravirt.c               | 2 +-
>  arch/x86/mm/mem_encrypt_identity.c       | 6 +++---
>  arch/x86/xen/enlighten_pv.c              | 4 ++--
>  7 files changed, 15 insertions(+), 15 deletions(-)
> 
> diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
> index f054bf52c10a..4b617f8f9b7f 100644
> --- a/arch/x86/boot/compressed/sev.c
> +++ b/arch/x86/boot/compressed/sev.c
> @@ -494,7 +494,7 @@ static int sev_check_cpu_support(void)
>  	/* Check for the SME/SEV support leaf */
>  	eax = 0x80000000;
>  	ecx = 0;
> -	native_cpuid(&eax, &ebx, &ecx, &edx);
> +	cpuid_native(&eax, &ebx, &ecx, &edx);
>  	if (eax < 0x8000001f)
>  		return -ENODEV;

I'm torn about this one.

native_*() is a pretty generic way to denote baremetal methods, all 
around the x86 tree:

  starship:~/tip> git grep -E '\<native_' arch/x86/ | wc -l
  682

Likewise for:

	native_cpuid_eax()
	native_cpuid_ebx()
	native_cpuid_ecx()
	native_cpuid_edx()

I think it might be better to leave these as native_cpuid_*, because 
shifting a naming inconsistency into another namespace isn't really a 
net improvement.

'git grep cpuid_eax' will still give meaningful results, so 
greppability of cpuid_ APIs only suffers somewhat. The for_each_cpuid_ 
methods are already outliers.

There's always a bigger fish^W prefix. ;-)

Thanks,

	Ingo

[tip: x86/core] x86/cpu/intel: Rename CPUID(0x2) descriptors iterator parameter

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     234792ea4421499f123e73b2e6411469a561a123
Gitweb:        https://git.kernel.org/tip/234792ea4421499f123e73b2e6411469a561a123
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:36 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 15 May 2025 18:48:10 +02:00

x86/cpu/intel: Rename CPUID(0x2) descriptors iterator parameter

The CPUID(0x2) descriptors iterator has been renamed from:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

since it iterates over CPUID(0x2) cache and TLB "descriptors", not
"entries".

In the macro's x86/cpu call-site, rename the parameter denoting the
parsed descriptor at each iteration from 'entry' to 'desc'.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-8-darwi@linutronix.de
---
 arch/x86/kernel/cpu/intel.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index f8141b5..076eaa4 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -648,11 +648,11 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 }
 #endif
 
-static void intel_tlb_lookup(const struct leaf_0x2_table *entry)
+static void intel_tlb_lookup(const struct leaf_0x2_table *desc)
 {
-	short entries = entry->entries;
+	short entries = desc->entries;
 
-	switch (entry->t_type) {
+	switch (desc->t_type) {
 	case STLB_4K:
 		tlb_lli_4k = max(tlb_lli_4k, entries);
 		tlb_lld_4k = max(tlb_lld_4k, entries);
@@ -709,7 +709,7 @@ static void intel_tlb_lookup(const struct leaf_0x2_table *entry)
 
 static void intel_detect_tlb(struct cpuinfo_x86 *c)
 {
-	const struct leaf_0x2_table *entry;
+	const struct leaf_0x2_table *desc;
 	union leaf_0x2_regs regs;
 	u8 *ptr;
 
@@ -717,8 +717,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 		return;
 
 	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, entry)
-		intel_tlb_lookup(entry);
+	for_each_cpuid_0x2_desc(regs, ptr, desc)
+		intel_tlb_lookup(desc);
 }
 
 static const struct cpu_dev intel_cpu_dev = {

[tip: x86/core] x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     7f6b49644c6cadd9682075bc2dd6a1ba2afd55d8
Gitweb:        https://git.kernel.org/tip/7f6b49644c6cadd9682075bc2dd6a1ba2afd55d8
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:35 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 15 May 2025 18:48:10 +02:00

x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter

The CPUID(0x2) descriptors iterator has been renamed from:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

since it iterates over CPUID(0x2) cache and TLB "descriptors", not
"entries".

In the macro's x86/cacheinfo call-site, rename the parameter denoting the
parsed descriptor at each iteration from 'entry' to 'desc'.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-7-darwi@linutronix.de
---
 arch/x86/kernel/cpu/cacheinfo.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index b6349c1..adfa7e8 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -381,7 +381,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3,
 static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 {
 	unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0;
-	const struct leaf_0x2_table *entry;
+	const struct leaf_0x2_table *desc;
 	union leaf_0x2_regs regs;
 	u8 *ptr;
 
@@ -389,12 +389,12 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 		return;
 
 	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, entry) {
-		switch (entry->c_type) {
-		case CACHE_L1_INST:	l1i += entry->c_size; break;
-		case CACHE_L1_DATA:	l1d += entry->c_size; break;
-		case CACHE_L2:		l2  += entry->c_size; break;
-		case CACHE_L3:		l3  += entry->c_size; break;
+	for_each_cpuid_0x2_desc(regs, ptr, desc) {
+		switch (desc->c_type) {
+		case CACHE_L1_INST:	l1i += desc->c_size; break;
+		case CACHE_L1_DATA:	l1d += desc->c_size; break;
+		case CACHE_L2:		l2  += desc->c_size; break;
+		case CACHE_L3:		l3  += desc->c_size; break;
 		}
 	}
 

[tip: x86/core] x86/cpuid: Rename have_cpuid_p() to cpuid_feature()

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     2f924ca36d2f788d40a57ea48825ff51cba4e700
Gitweb:        https://git.kernel.org/tip/2f924ca36d2f788d40a57ea48825ff51cba4e700
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:32 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 15 May 2025 18:23:55 +02:00

x86/cpuid: Rename have_cpuid_p() to cpuid_feature()

In order to let all the APIs under <cpuid/api.h> have a shared "cpuid_"
namespace, rename have_cpuid_p() to cpuid_feature().

Adjust all call-sites accordingly.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-4-darwi@linutronix.de
---
 arch/x86/include/asm/cpuid/api.h     |  4 ++--
 arch/x86/kernel/cpu/common.c         | 10 +++++-----
 arch/x86/kernel/cpu/microcode/core.c |  2 +-
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index ff8891a..c0211fc 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -14,9 +14,9 @@
  */
 
 #ifdef CONFIG_X86_32
-bool have_cpuid_p(void);
+bool cpuid_feature(void);
 #else
-static inline bool have_cpuid_p(void)
+static inline bool cpuid_feature(void)
 {
 	return true;
 }
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index c14db8d..8feb8fd 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -322,7 +322,7 @@ static int __init cachesize_setup(char *str)
 __setup("cachesize=", cachesize_setup);
 
 /* Probe for the CPUID instruction */
-bool have_cpuid_p(void)
+bool cpuid_feature(void)
 {
 	return flag_is_changeable_p(X86_EFLAGS_ID);
 }
@@ -1711,11 +1711,11 @@ static void __init early_identify_cpu(struct cpuinfo_x86 *c)
 	memset(&c->x86_capability, 0, sizeof(c->x86_capability));
 	c->extended_cpuid_level = 0;
 
-	if (!have_cpuid_p())
+	if (!cpuid_feature())
 		identify_cpu_without_cpuid(c);
 
 	/* cyrix could have cpuid enabled via c_identify()*/
-	if (have_cpuid_p()) {
+	if (cpuid_feature()) {
 		cpu_detect(c);
 		get_cpu_vendor(c);
 		intel_unlock_cpuid_leafs(c);
@@ -1875,11 +1875,11 @@ static void generic_identify(struct cpuinfo_x86 *c)
 {
 	c->extended_cpuid_level = 0;
 
-	if (!have_cpuid_p())
+	if (!cpuid_feature())
 		identify_cpu_without_cpuid(c);
 
 	/* cyrix could have cpuid enabled via c_identify()*/
-	if (!have_cpuid_p())
+	if (!cpuid_feature())
 		return;
 
 	cpu_detect(c);
diff --git a/arch/x86/kernel/cpu/microcode/core.c b/arch/x86/kernel/cpu/microcode/core.c
index a3bcb6d..fe50eb5 100644
--- a/arch/x86/kernel/cpu/microcode/core.c
+++ b/arch/x86/kernel/cpu/microcode/core.c
@@ -118,7 +118,7 @@ bool __init microcode_loader_disabled(void)
 	 * 3) Certain AMD patch levels are not allowed to be
 	 *    overwritten.
 	 */
-	if (!have_cpuid_p() ||
+	if (!cpuid_feature() ||
 	    native_cpuid_ecx(1) & BIT(31) ||
 	    amd_check_current_patch_level())
 		dis_ucode_ldr = true;

[tip: x86/core] x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     c4c9ea879c3b22e812bf69cf94c5042f809a4ab0
Gitweb:        https://git.kernel.org/tip/c4c9ea879c3b22e812bf69cf94c5042f809a4ab0
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:34 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 15 May 2025 18:42:49 +02:00

x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()

Rename the CPUID(0x2) register accessor function:

    cpuid_get_leaf_0x2_regs(regs)

to:

    cpuid_leaf_0x2(regs)

for consistency with other <cpuid/api.h> accessors that return full CPUID
registers outputs like:

    cpuid_leaf(regs)
    cpuid_subleaf(regs)

In the same vein, rename the CPUID(0x2) iteration macro:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

to include "cpuid" in the macro name, and since what is iterated upon is
CPUID(0x2) cache and TLB "descriptos", not "entries".  Prefix an
underscore to that iterator macro parameters, so that the newly renamed
'desc' parameter do not get mixed with "union leaf_0x2_regs :: desc[]" in
the macro's implementation.

Adjust all the affected call-sites accordingly.

While at it, use "CPUID(0x2)" instead of "CPUID leaf 0x2" as this is the
recommended style.

No change in functionality intended.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-6-darwi@linutronix.de
---
 arch/x86/include/asm/cpuid/api.h | 34 +++++++++++++++----------------
 arch/x86/kernel/cpu/cacheinfo.c  |  4 ++--
 arch/x86/kernel/cpu/intel.c      |  4 ++--
 3 files changed, 21 insertions(+), 21 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index c0211fc..bf97f97 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -216,17 +216,17 @@ static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves)
  */
 
 /**
- * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
+ * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output
  * @regs:	Output parameter
  *
- * Query CPUID leaf 0x2 and store its output in @regs.	Force set any
+ * Query CPUID(0x2) and store its output in @regs.  Force set any
  * invalid 1-byte descriptor returned by the hardware to zero (the NULL
  * cache/TLB descriptor) before returning it to the caller.
  *
- * Use for_each_leaf_0x2_entry() to iterate over the register output in
+ * Use for_each_cpuid_0x2_desc() to iterate over the register output in
  * parsed form.
  */
-static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
+static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs)
 {
 	cpuid_leaf(0x2, regs);
 
@@ -251,34 +251,34 @@ static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
 }
 
 /**
- * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
- * @regs:   Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
+ * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
+ * @regs:   CPUID(0x2) register output, as returned by cpuid_leaf_0x2()
  * @__ptr:  u8 pointer, for macro internal use only
- * @entry:  Pointer to parsed descriptor information at each iteration
+ * @desc:   Pointer to parsed CPUID(0x2) descriptor at each iteration
  *
- * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
- * @regs.  Provide the parsed information for each descriptor through @entry.
+ * Loop over the 1-byte descriptors in the passed CPUID(0x2) output registers
+ * @regs.  Provide the parsed information for each descriptor through @desc.
  *
  * To handle cache-specific descriptors, switch on @entry->c_type.  For TLB
  * descriptors, switch on @entry->t_type.
  *
  * Example usage for cache descriptors::
  *
- *	const struct leaf_0x2_table *entry;
+ *	const struct leaf_0x2_table *desc;
  *	union leaf_0x2_regs regs;
  *	u8 *ptr;
  *
- *	cpuid_get_leaf_0x2_regs(&regs);
- *	for_each_leaf_0x2_entry(regs, ptr, entry) {
- *		switch (entry->c_type) {
+ *	cpuid_leaf_0x2(&regs);
+ *	for_each_cpuid_0x2_desc(regs, ptr, desc) {
+ *		switch (desc->c_type) {
  *			...
  *		}
  *	}
  */
-#define for_each_leaf_0x2_entry(regs, __ptr, entry)				\
-	for (__ptr = &(regs).desc[1];						\
-	     __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]);	\
-	     __ptr++)
+#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc)				\
+	for (_ptr = &(_regs).desc[1];						\
+	     _ptr < &(_regs).desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);	\
+	     _ptr++)
 
 /*
  * CPUID(0x80000006) parsing:
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 6d61f7d..b6349c1 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -388,8 +388,8 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 	if (c->cpuid_level < 2)
 		return;
 
-	cpuid_get_leaf_0x2_regs(&regs);
-	for_each_leaf_0x2_entry(regs, ptr, entry) {
+	cpuid_leaf_0x2(&regs);
+	for_each_cpuid_0x2_desc(regs, ptr, entry) {
 		switch (entry->c_type) {
 		case CACHE_L1_INST:	l1i += entry->c_size; break;
 		case CACHE_L1_DATA:	l1d += entry->c_size; break;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7f8ca29..f8141b5 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -716,8 +716,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 	if (c->cpuid_level < 2)
 		return;
 
-	cpuid_get_leaf_0x2_regs(&regs);
-	for_each_leaf_0x2_entry(regs, ptr, entry)
+	cpuid_leaf_0x2(&regs);
+	for_each_cpuid_0x2_desc(regs, ptr, entry)
 		intel_tlb_lookup(entry);
 }
 

[tip: x86/core] x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     968e3000680713f712bcf02c51c4d7bb7d4d7685
Gitweb:        https://git.kernel.org/tip/968e3000680713f712bcf02c51c4d7bb7d4d7685
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:31 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 15 May 2025 18:23:55 +02:00

x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header

The main CPUID header <asm/cpuid.h> was originally a storefront for the
headers:

    <asm/cpuid/api.h>
    <asm/cpuid/leaf_0x2_api.h>

Now that the latter CPUID(0x2) header has been merged into the former,
there is no practical difference between <asm/cpuid.h> and
<asm/cpuid/api.h>.

Migrate all users to the <asm/cpuid/api.h> header, in preparation of
the removal of <asm/cpuid.h>.

Don't remove <asm/cpuid.h> just yet, in case some new code in -next
started using it.

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-3-darwi@linutronix.de
---
 arch/x86/boot/compressed/sev.c        | 2 +-
 arch/x86/boot/startup/sev-startup.c   | 2 +-
 arch/x86/coco/sev/core.c              | 2 +-
 arch/x86/coco/sev/vc-handle.c         | 2 +-
 arch/x86/events/intel/pt.c            | 2 +-
 arch/x86/include/asm/processor.h      | 2 +-
 arch/x86/kernel/acpi/cstate.c         | 2 +-
 arch/x86/kernel/amd_nb.c              | 2 +-
 arch/x86/kernel/cpu/cacheinfo.c       | 2 +-
 arch/x86/kernel/cpu/common.c          | 2 +-
 arch/x86/kernel/cpu/intel.c           | 2 +-
 arch/x86/kernel/fpu/xstate.c          | 2 +-
 arch/x86/kernel/hpet.c                | 2 +-
 arch/x86/kernel/process.c             | 2 +-
 arch/x86/kernel/smpboot.c             | 2 +-
 arch/x86/kernel/tsc.c                 | 2 +-
 arch/x86/kvm/cpuid.c                  | 2 +-
 arch/x86/virt/svm/sev.c               | 2 +-
 arch/x86/xen/enlighten_pv.c           | 2 +-
 drivers/acpi/acpi_pad.c               | 2 +-
 drivers/dma/ioat/dca.c                | 2 +-
 drivers/idle/intel_idle.c             | 2 +-
 drivers/platform/x86/intel/pmc/core.c | 2 +-
 sound/soc/intel/avs/tgl.c             | 2 +-
 24 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
index 612b443..fd1b67d 100644
--- a/arch/x86/boot/compressed/sev.c
+++ b/arch/x86/boot/compressed/sev.c
@@ -21,7 +21,7 @@
 #include <asm/fpu/xcr.h>
 #include <asm/ptrace.h>
 #include <asm/svm.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 
 #include "error.h"
 #include "sev.h"
diff --git a/arch/x86/boot/startup/sev-startup.c b/arch/x86/boot/startup/sev-startup.c
index 435853a..0b7e3b9 100644
--- a/arch/x86/boot/startup/sev-startup.c
+++ b/arch/x86/boot/startup/sev-startup.c
@@ -38,7 +38,7 @@
 #include <asm/smp.h>
 #include <asm/cpu.h>
 #include <asm/apic.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cmdline.h>
 
 /* For early boot hypervisor communication in SEV-ES enabled guests */
diff --git a/arch/x86/coco/sev/core.c b/arch/x86/coco/sev/core.c
index b40c159..5678c3f 100644
--- a/arch/x86/coco/sev/core.c
+++ b/arch/x86/coco/sev/core.c
@@ -42,7 +42,7 @@
 #include <asm/smp.h>
 #include <asm/cpu.h>
 #include <asm/apic.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cmdline.h>
 #include <asm/msr.h>
 
diff --git a/arch/x86/coco/sev/vc-handle.c b/arch/x86/coco/sev/vc-handle.c
index b4895c6..0989d98 100644
--- a/arch/x86/coco/sev/vc-handle.c
+++ b/arch/x86/coco/sev/vc-handle.c
@@ -32,7 +32,7 @@
 #include <asm/smp.h>
 #include <asm/cpu.h>
 #include <asm/apic.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 
 static enum es_result vc_slow_virt_to_phys(struct ghcb *ghcb, struct es_em_ctxt *ctxt,
 					   unsigned long vaddr, phys_addr_t *paddr)
diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index f37cce2..9dbc688 100644
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -18,7 +18,7 @@
 #include <linux/slab.h>
 #include <linux/device.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/perf_event.h>
 #include <asm/insn.h>
 #include <asm/io.h>
diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/processor.h
index 50d3469..bde58f6 100644
--- a/arch/x86/include/asm/processor.h
+++ b/arch/x86/include/asm/processor.h
@@ -16,7 +16,7 @@ struct vm86;
 #include <uapi/asm/sigcontext.h>
 #include <asm/current.h>
 #include <asm/cpufeatures.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/page.h>
 #include <asm/pgtable_types.h>
 #include <asm/percpu.h>
diff --git a/arch/x86/kernel/acpi/cstate.c b/arch/x86/kernel/acpi/cstate.c
index d5ac341..8698d66 100644
--- a/arch/x86/kernel/acpi/cstate.c
+++ b/arch/x86/kernel/acpi/cstate.c
@@ -14,7 +14,7 @@
 
 #include <acpi/processor.h>
 #include <asm/cpu_device_id.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/mwait.h>
 #include <asm/special_insns.h>
 #include <asm/smp.h>
diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c
index 7c79c9f..c1acead 100644
--- a/arch/x86/kernel/amd_nb.c
+++ b/arch/x86/kernel/amd_nb.c
@@ -15,7 +15,7 @@
 #include <linux/pci_ids.h>
 
 #include <asm/amd/nb.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 
 static u32 *flush_words;
 
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index f866d94..6d61f7d 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -16,7 +16,7 @@
 #include <asm/amd/nb.h>
 #include <asm/cacheinfo.h>
 #include <asm/cpufeature.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/mtrr.h>
 #include <asm/smp.h>
 #include <asm/tlbflush.h>
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index 114aaaf..c14db8d 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -29,7 +29,7 @@
 
 #include <asm/alternative.h>
 #include <asm/cmdline.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/perf_event.h>
 #include <asm/mmu_context.h>
 #include <asm/doublefault.h>
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 584dd55..7f8ca29 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -16,7 +16,7 @@
 #include <asm/cpu_device_id.h>
 #include <asm/cpufeature.h>
 #include <asm/cpu.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/hwcap2.h>
 #include <asm/intel-family.h>
 #include <asm/microcode.h>
diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
index 3e477a5..9aa9ac8 100644
--- a/arch/x86/kernel/fpu/xstate.c
+++ b/arch/x86/kernel/fpu/xstate.c
@@ -21,7 +21,7 @@
 #include <asm/fpu/signal.h>
 #include <asm/fpu/xcr.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/msr.h>
 #include <asm/tlbflush.h>
 #include <asm/prctl.h>
diff --git a/arch/x86/kernel/hpet.c b/arch/x86/kernel/hpet.c
index c9982a7..d6387dd 100644
--- a/arch/x86/kernel/hpet.c
+++ b/arch/x86/kernel/hpet.c
@@ -7,7 +7,7 @@
 #include <linux/cpu.h>
 #include <linux/irq.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/irq_remapping.h>
 #include <asm/hpet.h>
 #include <asm/time.h>
diff --git a/arch/x86/kernel/process.c b/arch/x86/kernel/process.c
index 4b668bc..c1d2dac 100644
--- a/arch/x86/kernel/process.c
+++ b/arch/x86/kernel/process.c
@@ -30,7 +30,7 @@
 #include <linux/hw_breakpoint.h>
 #include <linux/entry-common.h>
 #include <asm/cpu.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/apic.h>
 #include <linux/uaccess.h>
 #include <asm/mwait.h>
diff --git a/arch/x86/kernel/smpboot.c b/arch/x86/kernel/smpboot.c
index d6cf1e2..d7d61b3 100644
--- a/arch/x86/kernel/smpboot.c
+++ b/arch/x86/kernel/smpboot.c
@@ -64,7 +64,7 @@
 
 #include <asm/acpi.h>
 #include <asm/cacheinfo.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/desc.h>
 #include <asm/nmi.h>
 #include <asm/irq.h>
diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c
index 5d3a764..87e7491 100644
--- a/arch/x86/kernel/tsc.c
+++ b/arch/x86/kernel/tsc.c
@@ -16,7 +16,7 @@
 #include <linux/static_key.h>
 #include <linux/static_call.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/hpet.h>
 #include <asm/timer.h>
 #include <asm/vgtod.h>
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 571c906..7f43d8d 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -21,7 +21,7 @@
 #include <asm/user.h>
 #include <asm/fpu/xstate.h>
 #include <asm/sgx.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include "cpuid.h"
 #include "lapic.h"
 #include "mmu.h"
diff --git a/arch/x86/virt/svm/sev.c b/arch/x86/virt/svm/sev.c
index 76926f7..942372e 100644
--- a/arch/x86/virt/svm/sev.c
+++ b/arch/x86/virt/svm/sev.c
@@ -27,7 +27,7 @@
 #include <asm/smp.h>
 #include <asm/cpu.h>
 #include <asm/apic.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cmdline.h>
 #include <asm/iommu.h>
 #include <asm/msr.h>
diff --git a/arch/x86/xen/enlighten_pv.c b/arch/x86/xen/enlighten_pv.c
index 3be3835..7f9ded1 100644
--- a/arch/x86/xen/enlighten_pv.c
+++ b/arch/x86/xen/enlighten_pv.c
@@ -49,7 +49,7 @@
 #include <xen/hvc-console.h>
 #include <xen/acpi.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/paravirt.h>
 #include <asm/apic.h>
 #include <asm/page.h>
diff --git a/drivers/acpi/acpi_pad.c b/drivers/acpi/acpi_pad.c
index 3fde449..6f8bbe1 100644
--- a/drivers/acpi/acpi_pad.c
+++ b/drivers/acpi/acpi_pad.c
@@ -19,7 +19,7 @@
 #include <linux/acpi.h>
 #include <linux/perf_event.h>
 #include <linux/platform_device.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/mwait.h>
 #include <xen/xen.h>
 
diff --git a/drivers/dma/ioat/dca.c b/drivers/dma/ioat/dca.c
index c9aba23..5d3c0ae 100644
--- a/drivers/dma/ioat/dca.c
+++ b/drivers/dma/ioat/dca.c
@@ -10,7 +10,7 @@
 #include <linux/interrupt.h>
 #include <linux/dca.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 
 /* either a kernel change is needed, or we need something like this in kernel */
 #ifndef CONFIG_SMP
diff --git a/drivers/idle/intel_idle.c b/drivers/idle/intel_idle.c
index 6a1712b..433d858 100644
--- a/drivers/idle/intel_idle.c
+++ b/drivers/idle/intel_idle.c
@@ -51,7 +51,7 @@
 #include <linux/notifier.h>
 #include <linux/cpu.h>
 #include <linux/moduleparam.h>
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cpu_device_id.h>
 #include <asm/intel-family.h>
 #include <asm/mwait.h>
diff --git a/drivers/platform/x86/intel/pmc/core.c b/drivers/platform/x86/intel/pmc/core.c
index ff7f64d..9f678c7 100644
--- a/drivers/platform/x86/intel/pmc/core.c
+++ b/drivers/platform/x86/intel/pmc/core.c
@@ -22,7 +22,7 @@
 #include <linux/suspend.h>
 #include <linux/units.h>
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 #include <asm/cpu_device_id.h>
 #include <asm/intel-family.h>
 #include <asm/msr.h>
diff --git a/sound/soc/intel/avs/tgl.c b/sound/soc/intel/avs/tgl.c
index 56905f2..9dbb3ad 100644
--- a/sound/soc/intel/avs/tgl.c
+++ b/sound/soc/intel/avs/tgl.c
@@ -47,7 +47,7 @@ static int avs_tgl_config_basefw(struct avs_dev *adev)
 #ifdef CONFIG_X86
 	unsigned int ecx;
 
-#include <asm/cpuid.h>
+#include <asm/cpuid/api.h>
 	ecx = cpuid_ecx(CPUID_TSC_LEAF);
 	if (ecx) {
 		ret = avs_ipc_set_fw_config(adev, 1, AVS_FW_CFG_XTAL_FREQ_HZ, sizeof(ecx), &ecx);

[tip: x86/core] x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     cdc8be31cb324a0c52529f192e39a44abcfff513
Gitweb:        https://git.kernel.org/tip/cdc8be31cb324a0c52529f192e39a44abcfff513
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:30 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Thu, 15 May 2025 18:23:54 +02:00

x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>

Move all of the CPUID(0x2) APIs at <cpuid/leaf_0x2_api.h> into
<cpuid/api.h>, in order centralize all CPUID APIs into the latter.

While at it, separate the different CPUID leaf parsing APIs using
header comments like "CPUID(0xN) parsing: ".

Suggested-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-2-darwi@linutronix.de
---
 arch/x86/include/asm/cpuid.h              |  1 +-
 arch/x86/include/asm/cpuid/api.h          | 75 +++++++++++++++++++++-
 arch/x86/include/asm/cpuid/leaf_0x2_api.h | 73 +---------------------
 arch/x86/include/asm/cpuid/types.h        |  3 +-
 4 files changed, 75 insertions(+), 77 deletions(-)
 delete mode 100644 arch/x86/include/asm/cpuid/leaf_0x2_api.h

diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h
index 5858193..d5749b2 100644
--- a/arch/x86/include/asm/cpuid.h
+++ b/arch/x86/include/asm/cpuid.h
@@ -4,6 +4,5 @@
 #define _ASM_X86_CPUID_H
 
 #include <asm/cpuid/api.h>
-#include <asm/cpuid/leaf_0x2_api.h>
 
 #endif /* _ASM_X86_CPUID_H */
diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index bf76a17..ff8891a 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -160,6 +160,10 @@ static inline void __cpuid_read_reg(u32 leaf, u32 subleaf,
 	__cpuid_read_reg(leaf, 0, regidx, (u32 *)(reg));	\
 }
 
+/*
+ * Hypervisor-related APIs:
+ */
+
 static __always_inline bool cpuid_function_is_indexed(u32 function)
 {
 	switch (function) {
@@ -208,7 +212,76 @@ static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves)
 }
 
 /*
- * CPUID(0x80000006) parsing helpers
+ * CPUID(0x2) parsing:
+ */
+
+/**
+ * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
+ * @regs:	Output parameter
+ *
+ * Query CPUID leaf 0x2 and store its output in @regs.	Force set any
+ * invalid 1-byte descriptor returned by the hardware to zero (the NULL
+ * cache/TLB descriptor) before returning it to the caller.
+ *
+ * Use for_each_leaf_0x2_entry() to iterate over the register output in
+ * parsed form.
+ */
+static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
+{
+	cpuid_leaf(0x2, regs);
+
+	/*
+	 * All Intel CPUs must report an iteration count of 1.	In case
+	 * of bogus hardware, treat all returned descriptors as NULL.
+	 */
+	if (regs->desc[0] != 0x01) {
+		for (int i = 0; i < 4; i++)
+			regs->regv[i] = 0;
+		return;
+	}
+
+	/*
+	 * The most significant bit (MSB) of each register must be clear.
+	 * If a register is invalid, replace its descriptors with NULL.
+	 */
+	for (int i = 0; i < 4; i++) {
+		if (regs->reg[i].invalid)
+			regs->regv[i] = 0;
+	}
+}
+
+/**
+ * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
+ * @regs:   Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
+ * @__ptr:  u8 pointer, for macro internal use only
+ * @entry:  Pointer to parsed descriptor information at each iteration
+ *
+ * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
+ * @regs.  Provide the parsed information for each descriptor through @entry.
+ *
+ * To handle cache-specific descriptors, switch on @entry->c_type.  For TLB
+ * descriptors, switch on @entry->t_type.
+ *
+ * Example usage for cache descriptors::
+ *
+ *	const struct leaf_0x2_table *entry;
+ *	union leaf_0x2_regs regs;
+ *	u8 *ptr;
+ *
+ *	cpuid_get_leaf_0x2_regs(&regs);
+ *	for_each_leaf_0x2_entry(regs, ptr, entry) {
+ *		switch (entry->c_type) {
+ *			...
+ *		}
+ *	}
+ */
+#define for_each_leaf_0x2_entry(regs, __ptr, entry)				\
+	for (__ptr = &(regs).desc[1];						\
+	     __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]);	\
+	     __ptr++)
+
+/*
+ * CPUID(0x80000006) parsing:
  */
 
 static inline bool cpuid_amd_hygon_has_l3_cache(void)
diff --git a/arch/x86/include/asm/cpuid/leaf_0x2_api.h b/arch/x86/include/asm/cpuid/leaf_0x2_api.h
deleted file mode 100644
index 09fa307..0000000
--- a/arch/x86/include/asm/cpuid/leaf_0x2_api.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef _ASM_X86_CPUID_LEAF_0x2_API_H
-#define _ASM_X86_CPUID_LEAF_0x2_API_H
-
-#include <asm/cpuid/api.h>
-#include <asm/cpuid/types.h>
-
-/**
- * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
- * @regs:	Output parameter
- *
- * Query CPUID leaf 0x2 and store its output in @regs.	Force set any
- * invalid 1-byte descriptor returned by the hardware to zero (the NULL
- * cache/TLB descriptor) before returning it to the caller.
- *
- * Use for_each_leaf_0x2_entry() to iterate over the register output in
- * parsed form.
- */
-static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
-{
-	cpuid_leaf(0x2, regs);
-
-	/*
-	 * All Intel CPUs must report an iteration count of 1.	In case
-	 * of bogus hardware, treat all returned descriptors as NULL.
-	 */
-	if (regs->desc[0] != 0x01) {
-		for (int i = 0; i < 4; i++)
-			regs->regv[i] = 0;
-		return;
-	}
-
-	/*
-	 * The most significant bit (MSB) of each register must be clear.
-	 * If a register is invalid, replace its descriptors with NULL.
-	 */
-	for (int i = 0; i < 4; i++) {
-		if (regs->reg[i].invalid)
-			regs->regv[i] = 0;
-	}
-}
-
-/**
- * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
- * @regs:   Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
- * @__ptr:  u8 pointer, for macro internal use only
- * @entry:  Pointer to parsed descriptor information at each iteration
- *
- * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
- * @regs.  Provide the parsed information for each descriptor through @entry.
- *
- * To handle cache-specific descriptors, switch on @entry->c_type.  For TLB
- * descriptors, switch on @entry->t_type.
- *
- * Example usage for cache descriptors::
- *
- *	const struct leaf_0x2_table *entry;
- *	union leaf_0x2_regs regs;
- *	u8 *ptr;
- *
- *	cpuid_get_leaf_0x2_regs(&regs);
- *	for_each_leaf_0x2_entry(regs, ptr, entry) {
- *		switch (entry->c_type) {
- *			...
- *		}
- *	}
- */
-#define for_each_leaf_0x2_entry(regs, __ptr, entry)				\
-	for (__ptr = &(regs).desc[1];						\
-	     __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]);	\
-	     __ptr++)
-
-#endif /* _ASM_X86_CPUID_LEAF_0x2_API_H */
diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpuid/types.h
index c95fee6..8a00364 100644
--- a/arch/x86/include/asm/cpuid/types.h
+++ b/arch/x86/include/asm/cpuid/types.h
@@ -31,8 +31,7 @@ enum cpuid_regs_idx {
 #define CPUID_LEAF_TILE		0x1d
 
 /*
- * Types for CPUID(0x2) parsing
- * Check <asm/cpuid/leaf_0x2_api.h>
+ * Types for CPUID(0x2) parsing:
  */
 
 struct leaf_0x2_reg {

Re: [PATCH v1 2/9] x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header

[Ahmed S. Darwish]

On Thu, 15 May 2025, Ingo Molnar wrote:
>
> Note that in the tip:x86/core commit I've applied today I've delayed
> this removal of <asm/cpuid.h>, in case there's something in -next that
> started using it. I've adjusted the changelog accordingly.
>
> We can remove it later on, shortly after -rc1 or so.
>

Yup, thanks a lot.

Re: [PATCH v1 4/9] x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()

[Ahmed S. Darwish]

On Thu, 15 May 2025, Ingo Molnar wrote:
>
> So the interaction here looks a bit weird IMO (what is a 'hypervisor
> base'?), and I think the 'CPUID base' phrase should be immutable.
>
> Ie. I think it would be more natural to call this method
> cpuid_base_hypervisor(), which would mix reasonably well with:
>
> 	kvm_cpuid_base()
> 	xen_cpuid_base()
> 	jailhouse_cpuid_base()
>
> These lower level methods are prefixed with kvm_/xen_/jailhouse_, as
> most of their internal methods are.
>
> Likewise, for_each_possible_cpuid_base_hypervisor()?
>

Makes sense; will do.

Re: [PATCH v1 8/9] x86/cpuid: Rename native_cpuid() to cpuid_native()

[Ahmed S. Darwish]

On Thu, 15 May 2025, Ingo Molnar wrote:
>
> * Ahmed S. Darwish <darwi@linutronix.de> wrote:
> >
> > diff --git a/arch/x86/boot/compressed/sev.c b/arch/x86/boot/compressed/sev.c
> > index f054bf52c10a..4b617f8f9b7f 100644
> > --- a/arch/x86/boot/compressed/sev.c
> > +++ b/arch/x86/boot/compressed/sev.c
> > @@ -494,7 +494,7 @@ static int sev_check_cpu_support(void)
> >  	/* Check for the SME/SEV support leaf */
> >  	eax = 0x80000000;
> >  	ecx = 0;
> > -	native_cpuid(&eax, &ebx, &ecx, &edx);
> > +	cpuid_native(&eax, &ebx, &ecx, &edx);
> >  	if (eax < 0x8000001f)
> >  		return -ENODEV;
>
> I'm torn about this one.
>
> native_*() is a pretty generic way to denote baremetal methods, all
> around the x86 tree:
>
>   starship:~/tip> git grep -E '\<native_' arch/x86/ | wc -l
>   682
...
>
> I think it might be better to leave these as native_cpuid_*, because
> shifting a naming inconsistency into another namespace isn't really a
> net improvement.
>

Yeah, I admit I was a little bit uncomfortable about this one, especially
when modifying a call-site like:

    => arch/x86/kernel/paravirt.c:
    struct paravirt_patch_template pv_ops = {
	.cpu.io_delay		= native_io_delay,
	.cpu.cpuid		= cpuid_native,		// stands out
	.cpu.read_cr0		= native_read_cr0,
	.cpu.write_cr0		= native_write_cr0,
	.cpu.write_cr4		= native_write_cr4,
	.cpu.read_msr		= native_read_msr,
	...
    };

So, indeed, ACK.

Thanks!
~ Ahmed

Re: [PATCH v1 0/9] x86/cpuid: Headers cleanup

[Ahmed S. Darwish]

On Thu, 15 May 2025, Ingo Molnar wrote:
>
> Thank you for doing this. I've reviewed the series and applied these:
>
>     x86/cpuid: Move CPUID(0x2) APIs into <cpuid/api.h>
>     x86/cpuid: Set <asm/cpuid/api.h> as the main CPUID header
>     x86/cpuid: Rename have_cpuid_p() to cpuid_feature()
>     x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()
>     x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter
>     x86/cpu/intel: Rename CPUID(0x2) descriptors iterator parameter
>
> I had some questions about:
>
>     x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()
>     x86/cpuid: Rename native_cpuid() to cpuid_native()
>
> and you had better ideas about:
>
>     x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()
>

Thanks a lot for all the support as usual :)

I'll send a v2 then for the single one left:

    x86/cpuid: Rename hypervisor_cpuid_base() to cpuid_hypervisor_base()

and indeed drop:

   x86/cpuid: Rename native_cpuid() to cpuid_native()
   x86/cpuid: Rename native_cpuid_REG() to cpuid_native_REG()

All the best,
~ Ahmed

[tip: x86/core] x86/cpu/intel: Rename CPUID(0x2) descriptors iterator parameter

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     119deb95b0bc2793d4b002549444ce0aec346b4f
Gitweb:        https://git.kernel.org/tip/119deb95b0bc2793d4b002549444ce0aec346b4f
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:36 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 16 May 2025 10:49:55 +02:00

x86/cpu/intel: Rename CPUID(0x2) descriptors iterator parameter

The CPUID(0x2) descriptors iterator has been renamed from:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

since it iterates over CPUID(0x2) cache and TLB "descriptors", not
"entries".

In the macro's x86/cpu call-site, rename the parameter denoting the
parsed descriptor at each iteration from 'entry' to 'desc'.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-8-darwi@linutronix.de
---
 arch/x86/kernel/cpu/intel.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index f8141b5..076eaa4 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -648,11 +648,11 @@ static unsigned int intel_size_cache(struct cpuinfo_x86 *c, unsigned int size)
 }
 #endif
 
-static void intel_tlb_lookup(const struct leaf_0x2_table *entry)
+static void intel_tlb_lookup(const struct leaf_0x2_table *desc)
 {
-	short entries = entry->entries;
+	short entries = desc->entries;
 
-	switch (entry->t_type) {
+	switch (desc->t_type) {
 	case STLB_4K:
 		tlb_lli_4k = max(tlb_lli_4k, entries);
 		tlb_lld_4k = max(tlb_lld_4k, entries);
@@ -709,7 +709,7 @@ static void intel_tlb_lookup(const struct leaf_0x2_table *entry)
 
 static void intel_detect_tlb(struct cpuinfo_x86 *c)
 {
-	const struct leaf_0x2_table *entry;
+	const struct leaf_0x2_table *desc;
 	union leaf_0x2_regs regs;
 	u8 *ptr;
 
@@ -717,8 +717,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 		return;
 
 	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, entry)
-		intel_tlb_lookup(entry);
+	for_each_cpuid_0x2_desc(regs, ptr, desc)
+		intel_tlb_lookup(desc);
 }
 
 static const struct cpu_dev intel_cpu_dev = {

[tip: x86/core] x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     4b21e71ad6cc93d39d78176de269a0dc9a318fc6
Gitweb:        https://git.kernel.org/tip/4b21e71ad6cc93d39d78176de269a0dc9a318fc6
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:35 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 16 May 2025 10:49:55 +02:00

x86/cacheinfo: Rename CPUID(0x2) descriptors iterator parameter

The CPUID(0x2) descriptors iterator has been renamed from:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

since it iterates over CPUID(0x2) cache and TLB "descriptors", not
"entries".

In the macro's x86/cacheinfo call-site, rename the parameter denoting the
parsed descriptor at each iteration from 'entry' to 'desc'.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-7-darwi@linutronix.de
---
 arch/x86/kernel/cpu/cacheinfo.c | 14 +++++++-------
 1 file changed, 7 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index b6349c1..adfa7e8 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -381,7 +381,7 @@ static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3,
 static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 {
 	unsigned int l1i = 0, l1d = 0, l2 = 0, l3 = 0;
-	const struct leaf_0x2_table *entry;
+	const struct leaf_0x2_table *desc;
 	union leaf_0x2_regs regs;
 	u8 *ptr;
 
@@ -389,12 +389,12 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 		return;
 
 	cpuid_leaf_0x2(&regs);
-	for_each_cpuid_0x2_desc(regs, ptr, entry) {
-		switch (entry->c_type) {
-		case CACHE_L1_INST:	l1i += entry->c_size; break;
-		case CACHE_L1_DATA:	l1d += entry->c_size; break;
-		case CACHE_L2:		l2  += entry->c_size; break;
-		case CACHE_L3:		l3  += entry->c_size; break;
+	for_each_cpuid_0x2_desc(regs, ptr, desc) {
+		switch (desc->c_type) {
+		case CACHE_L1_INST:	l1i += desc->c_size; break;
+		case CACHE_L1_DATA:	l1d += desc->c_size; break;
+		case CACHE_L2:		l2  += desc->c_size; break;
+		case CACHE_L3:		l3  += desc->c_size; break;
 		}
 	}
 

[tip: x86/core] x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()

[tip-bot2 for Ahmed S. Darwish]

The following commit has been merged into the x86/core branch of tip:

Commit-ID:     e7df7289f1481993c9f326aea801323a1d3d0c5f
Gitweb:        https://git.kernel.org/tip/e7df7289f1481993c9f326aea801323a1d3d0c5f
Author:        Ahmed S. Darwish <darwi@linutronix.de>
AuthorDate:    Thu, 08 May 2025 17:02:34 +02:00
Committer:     Ingo Molnar <mingo@kernel.org>
CommitterDate: Fri, 16 May 2025 10:49:48 +02:00

x86/cpuid: Rename cpuid_get_leaf_0x2_regs() to cpuid_leaf_0x2()

Rename the CPUID(0x2) register accessor function:

    cpuid_get_leaf_0x2_regs(regs)

to:

    cpuid_leaf_0x2(regs)

for consistency with other <cpuid/api.h> accessors that return full CPUID
registers outputs like:

    cpuid_leaf(regs)
    cpuid_subleaf(regs)

In the same vein, rename the CPUID(0x2) iteration macro:

    for_each_leaf_0x2_entry()

to:

    for_each_cpuid_0x2_desc()

to include "cpuid" in the macro name, and since what is iterated upon is
CPUID(0x2) cache and TLB "descriptos", not "entries".  Prefix an
underscore to that iterator macro parameters, so that the newly renamed
'desc' parameter do not get mixed with "union leaf_0x2_regs :: desc[]" in
the macro's implementation.

Adjust all the affected call-sites accordingly.

While at it, use "CPUID(0x2)" instead of "CPUID leaf 0x2" as this is the
recommended style.

No change in functionality intended.

Signed-off-by: Ahmed S. Darwish <darwi@linutronix.de>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: John Ogness <john.ogness@linutronix.de>
Cc: x86-cpuid@lists.linux.dev
Link: https://lore.kernel.org/r/20250508150240.172915-6-darwi@linutronix.de
---
 arch/x86/include/asm/cpuid/api.h | 40 +++++++++++++++----------------
 arch/x86/kernel/cpu/cacheinfo.c  |  4 +--
 arch/x86/kernel/cpu/intel.c      |  4 +--
 3 files changed, 24 insertions(+), 24 deletions(-)

diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/api.h
index c0211fc..ccf20c6 100644
--- a/arch/x86/include/asm/cpuid/api.h
+++ b/arch/x86/include/asm/cpuid/api.h
@@ -216,17 +216,17 @@ static inline u32 hypervisor_cpuid_base(const char *sig, u32 leaves)
  */
 
 /**
- * cpuid_get_leaf_0x2_regs() - Return sanitized leaf 0x2 register output
+ * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output
  * @regs:	Output parameter
  *
- * Query CPUID leaf 0x2 and store its output in @regs.	Force set any
+ * Query CPUID(0x2) and store its output in @regs.  Force set any
  * invalid 1-byte descriptor returned by the hardware to zero (the NULL
  * cache/TLB descriptor) before returning it to the caller.
  *
- * Use for_each_leaf_0x2_entry() to iterate over the register output in
+ * Use for_each_cpuid_0x2_desc() to iterate over the register output in
  * parsed form.
  */
-static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
+static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs)
 {
 	cpuid_leaf(0x2, regs);
 
@@ -251,34 +251,34 @@ static inline void cpuid_get_leaf_0x2_regs(union leaf_0x2_regs *regs)
 }
 
 /**
- * for_each_leaf_0x2_entry() - Iterator for parsed leaf 0x2 descriptors
- * @regs:   Leaf 0x2 register output, returned by cpuid_get_leaf_0x2_regs()
- * @__ptr:  u8 pointer, for macro internal use only
- * @entry:  Pointer to parsed descriptor information at each iteration
+ * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors
+ * @_regs:	CPUID(0x2) register output, as returned by cpuid_leaf_0x2()
+ * @_ptr:	u8 pointer, for macro internal use only
+ * @_desc:	Pointer to the parsed CPUID(0x2) descriptor at each iteration
  *
- * Loop over the 1-byte descriptors in the passed leaf 0x2 output registers
- * @regs.  Provide the parsed information for each descriptor through @entry.
+ * Loop over the 1-byte descriptors in the passed CPUID(0x2) output registers
+ * @_regs.  Provide the parsed information for each descriptor through @_desc.
  *
- * To handle cache-specific descriptors, switch on @entry->c_type.  For TLB
- * descriptors, switch on @entry->t_type.
+ * To handle cache-specific descriptors, switch on @_desc->c_type.  For TLB
+ * descriptors, switch on @_desc->t_type.
  *
  * Example usage for cache descriptors::
  *
- *	const struct leaf_0x2_table *entry;
+ *	const struct leaf_0x2_table *desc;
  *	union leaf_0x2_regs regs;
  *	u8 *ptr;
  *
- *	cpuid_get_leaf_0x2_regs(&regs);
- *	for_each_leaf_0x2_entry(regs, ptr, entry) {
- *		switch (entry->c_type) {
+ *	cpuid_leaf_0x2(&regs);
+ *	for_each_cpuid_0x2_desc(regs, ptr, desc) {
+ *		switch (desc->c_type) {
  *			...
  *		}
  *	}
  */
-#define for_each_leaf_0x2_entry(regs, __ptr, entry)				\
-	for (__ptr = &(regs).desc[1];						\
-	     __ptr < &(regs).desc[16] && (entry = &cpuid_0x2_table[*__ptr]);	\
-	     __ptr++)
+#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc)				\
+	for (_ptr = &(_regs).desc[1];						\
+	     _ptr < &(_regs).desc[16] && (_desc = &cpuid_0x2_table[*_ptr]);	\
+	     _ptr++)
 
 /*
  * CPUID(0x80000006) parsing:
diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinfo.c
index 6d61f7d..b6349c1 100644
--- a/arch/x86/kernel/cpu/cacheinfo.c
+++ b/arch/x86/kernel/cpu/cacheinfo.c
@@ -388,8 +388,8 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c)
 	if (c->cpuid_level < 2)
 		return;
 
-	cpuid_get_leaf_0x2_regs(&regs);
-	for_each_leaf_0x2_entry(regs, ptr, entry) {
+	cpuid_leaf_0x2(&regs);
+	for_each_cpuid_0x2_desc(regs, ptr, entry) {
 		switch (entry->c_type) {
 		case CACHE_L1_INST:	l1i += entry->c_size; break;
 		case CACHE_L1_DATA:	l1d += entry->c_size; break;
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 7f8ca29..f8141b5 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -716,8 +716,8 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c)
 	if (c->cpuid_level < 2)
 		return;
 
-	cpuid_get_leaf_0x2_regs(&regs);
-	for_each_leaf_0x2_entry(regs, ptr, entry)
+	cpuid_leaf_0x2(&regs);
+	for_each_cpuid_0x2_desc(regs, ptr, entry)
 		intel_tlb_lookup(entry);
 }