* [PATCH v4 0/3] Move duplicated instructions macros into asm/insn.h
@ 2025-05-16 14:08 Alexandre Ghiti
2025-05-16 14:08 ` [PATCH v4 1/3] riscv: Fix typo EXRACT -> EXTRACT Alexandre Ghiti
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Alexandre Ghiti @ 2025-05-16 14:08 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Alexandre Ghiti, Anup Patel,
Atish Patra, linux-riscv, linux-kernel, kvm, kvm-riscv
Cc: Alexandre Ghiti
The instructions parsing macros were duplicated and one of them had different
implementations, which is error prone.
So let's consolidate those macros in asm/insn.h.
v1: https://lore.kernel.org/linux-riscv/20250422082545.450453-1-alexghiti@rivosinc.com/
v2: https://lore.kernel.org/linux-riscv/20250508082215.88658-1-alexghiti@rivosinc.com/
v3: https://lore.kernel.org/linux-riscv/20250508125202.108613-1-alexghiti@rivosinc.com/
Changes in v4:
- Rebase on top of for-next (on top of 6.15-rc6)
Changes in v3:
- Fix patch 2 which caused build failures (linux riscv bot), but the
patchset is exactly the same as v2
Changes in v2:
- Rebase on top of 6.15-rc5
- Add RB tags
- Define RV_X() using RV_X_mask() (Clément)
- Remove unused defines (Clément)
- Fix tabulations (Drew)
Alexandre Ghiti (3):
riscv: Fix typo EXRACT -> EXTRACT
riscv: Strengthen duplicate and inconsistent definition of RV_X()
riscv: Move all duplicate insn parsing macros into asm/insn.h
arch/riscv/include/asm/insn.h | 206 ++++++++++++++++++++++---
arch/riscv/kernel/machine_kexec_file.c | 2 +-
arch/riscv/kernel/traps_misaligned.c | 144 +----------------
arch/riscv/kernel/vector.c | 2 +-
arch/riscv/kvm/vcpu_insn.c | 128 +--------------
5 files changed, 188 insertions(+), 294 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH v4 1/3] riscv: Fix typo EXRACT -> EXTRACT
2025-05-16 14:08 [PATCH v4 0/3] Move duplicated instructions macros into asm/insn.h Alexandre Ghiti
@ 2025-05-16 14:08 ` Alexandre Ghiti
2025-05-16 14:08 ` [PATCH v4 2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X() Alexandre Ghiti
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Alexandre Ghiti @ 2025-05-16 14:08 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Alexandre Ghiti, Anup Patel,
Atish Patra, linux-riscv, linux-kernel, kvm, kvm-riscv
Cc: Alexandre Ghiti, Philippe Mathieu-Daudé, Andrew Jones
Simply fix a typo.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/include/asm/insn.h | 2 +-
arch/riscv/kernel/vector.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 09fde95a5e8f..2a589a58b291 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -352,7 +352,7 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
RVFDQ_FL_FS_WIDTH_MASK); })
-#define RVV_EXRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
+#define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
/*
* Get the immediate from a J-type instruction.
diff --git a/arch/riscv/kernel/vector.c b/arch/riscv/kernel/vector.c
index 184f780c932d..901e67adf576 100644
--- a/arch/riscv/kernel/vector.c
+++ b/arch/riscv/kernel/vector.c
@@ -93,7 +93,7 @@ bool insn_is_vector(u32 insn_buf)
return true;
case RVV_OPCODE_VL:
case RVV_OPCODE_VS:
- width = RVV_EXRACT_VL_VS_WIDTH(insn_buf);
+ width = RVV_EXTRACT_VL_VS_WIDTH(insn_buf);
if (width == RVV_VL_VS_WIDTH_8 || width == RVV_VL_VS_WIDTH_16 ||
width == RVV_VL_VS_WIDTH_32 || width == RVV_VL_VS_WIDTH_64)
return true;
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X()
2025-05-16 14:08 [PATCH v4 0/3] Move duplicated instructions macros into asm/insn.h Alexandre Ghiti
2025-05-16 14:08 ` [PATCH v4 1/3] riscv: Fix typo EXRACT -> EXTRACT Alexandre Ghiti
@ 2025-05-16 14:08 ` Alexandre Ghiti
2025-05-19 12:43 ` Clément Léger
2025-05-16 14:08 ` [PATCH v4 3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h Alexandre Ghiti
2025-06-04 14:33 ` [PATCH v4 0/3] Move duplicated instructions " patchwork-bot+linux-riscv
3 siblings, 1 reply; 7+ messages in thread
From: Alexandre Ghiti @ 2025-05-16 14:08 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Alexandre Ghiti, Anup Patel,
Atish Patra, linux-riscv, linux-kernel, kvm, kvm-riscv
Cc: Alexandre Ghiti, Andrew Jones
RV_X() macro is defined in two different ways which is error prone.
So harmonize its first definition and add another macro RV_X_mask() for
the second one.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/include/asm/insn.h | 39 +++++++++++++-------------
arch/riscv/kernel/machine_kexec_file.c | 2 +-
arch/riscv/kernel/traps_misaligned.c | 2 +-
arch/riscv/kvm/vcpu_insn.c | 2 +-
4 files changed, 23 insertions(+), 22 deletions(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index 2a589a58b291..ac3e606feca2 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -288,43 +288,44 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
-#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
-#define RVC_X(X, s, mask) RV_X(X, s, mask)
+#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask))
+#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1))
+#define RVC_X(X, s, mask) RV_X_mask(X, s, mask)
#define RV_EXTRACT_RS1_REG(x) \
({typeof(x) x_ = (x); \
- (RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
+ (RV_X_mask(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
#define RV_EXTRACT_RD_REG(x) \
({typeof(x) x_ = (x); \
- (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
+ (RV_X_mask(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
#define RV_EXTRACT_UTYPE_IMM(x) \
({typeof(x) x_ = (x); \
- (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
+ (RV_X_mask(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
#define RV_EXTRACT_JTYPE_IMM(x) \
({typeof(x) x_ = (x); \
- (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
- (RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
- (RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
+ (RV_X_mask(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
+ (RV_X_mask(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
+ (RV_X_mask(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
(RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
#define RV_EXTRACT_ITYPE_IMM(x) \
({typeof(x) x_ = (x); \
- (RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
+ (RV_X_mask(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
(RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
#define RV_EXTRACT_BTYPE_IMM(x) \
({typeof(x) x_ = (x); \
- (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
- (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
- (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
+ (RV_X_mask(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
+ (RV_X_mask(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
+ (RV_X_mask(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
(RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
#define RVC_EXTRACT_C2_RS1_REG(x) \
({typeof(x) x_ = (x); \
- (RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
+ (RV_X_mask(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
#define RVC_EXTRACT_JTYPE_IMM(x) \
({typeof(x) x_ = (x); \
@@ -346,10 +347,10 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
(RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
#define RVG_EXTRACT_SYSTEM_CSR(x) \
- ({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
+ ({typeof(x) x_ = (x); RV_X_mask(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
#define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \
- ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
+ ({typeof(x) x_ = (x); RV_X_mask(x_, RVFDQ_FL_FS_WIDTH_OFF, \
RVFDQ_FL_FS_WIDTH_MASK); })
#define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
@@ -375,10 +376,10 @@ static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)
{
/* drop the old IMMs, all jal IMM bits sit at 31:12 */
*insn &= ~GENMASK(31, 12);
- *insn |= (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
- (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
- (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
- (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
+ *insn |= (RV_X_mask(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
+ (RV_X_mask(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
+ (RV_X_mask(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
+ (RV_X_mask(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
}
/*
diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c
index e36104af2e24..5c2ed4c396e9 100644
--- a/arch/riscv/kernel/machine_kexec_file.c
+++ b/arch/riscv/kernel/machine_kexec_file.c
@@ -15,6 +15,7 @@
#include <linux/memblock.h>
#include <linux/vmalloc.h>
#include <asm/setup.h>
+#include <asm/insn.h>
const struct kexec_file_ops * const kexec_file_loaders[] = {
&elf_kexec_ops,
@@ -109,7 +110,6 @@ static char *setup_kdump_cmdline(struct kimage *image, char *cmdline,
}
#endif
-#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
#define RISCV_IMM_BITS 12
#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
#define RISCV_CONST_HIGH_PART(x) \
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 77c788660223..ac8f479a3f9c 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -17,6 +17,7 @@
#include <asm/hwprobe.h>
#include <asm/cpufeature.h>
#include <asm/vector.h>
+#include <asm/insn.h>
#define INSN_MATCH_LB 0x3
#define INSN_MASK_LB 0x707f
@@ -112,7 +113,6 @@
#define SH_RS2 20
#define SH_RS2C 2
-#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
(RV_X(x, 10, 3) << 3) | \
(RV_X(x, 5, 1) << 6))
diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c
index 97dec18e6989..62cb2ab4b636 100644
--- a/arch/riscv/kvm/vcpu_insn.c
+++ b/arch/riscv/kvm/vcpu_insn.c
@@ -8,6 +8,7 @@
#include <linux/kvm_host.h>
#include <asm/cpufeature.h>
+#include <asm/insn.h>
#define INSN_OPCODE_MASK 0x007c
#define INSN_OPCODE_SHIFT 2
@@ -91,7 +92,6 @@
#define SH_RS2C 2
#define MASK_RX 0x1f
-#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
(RV_X(x, 10, 3) << 3) | \
(RV_X(x, 5, 1) << 6))
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v4 3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h
2025-05-16 14:08 [PATCH v4 0/3] Move duplicated instructions macros into asm/insn.h Alexandre Ghiti
2025-05-16 14:08 ` [PATCH v4 1/3] riscv: Fix typo EXRACT -> EXTRACT Alexandre Ghiti
2025-05-16 14:08 ` [PATCH v4 2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X() Alexandre Ghiti
@ 2025-05-16 14:08 ` Alexandre Ghiti
2025-05-19 12:44 ` Clément Léger
2025-06-04 14:33 ` [PATCH v4 0/3] Move duplicated instructions " patchwork-bot+linux-riscv
3 siblings, 1 reply; 7+ messages in thread
From: Alexandre Ghiti @ 2025-05-16 14:08 UTC (permalink / raw)
To: Paul Walmsley, Palmer Dabbelt, Alexandre Ghiti, Anup Patel,
Atish Patra, linux-riscv, linux-kernel, kvm, kvm-riscv
Cc: Alexandre Ghiti, Andrew Jones
kernel/traps_misaligned.c and kvm/vcpu_insn.c define the same macros to
extract information from the instructions.
Let's move the definitions into asm/insn.h to avoid this duplication.
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/include/asm/insn.h | 171 ++++++++++++++++++++++++++-
arch/riscv/kernel/traps_misaligned.c | 142 ----------------------
arch/riscv/kvm/vcpu_insn.c | 126 --------------------
3 files changed, 166 insertions(+), 273 deletions(-)
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
index ac3e606feca2..ad26f859cfe5 100644
--- a/arch/riscv/include/asm/insn.h
+++ b/arch/riscv/include/asm/insn.h
@@ -286,11 +286,172 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
(code & RVC_INSN_J_RS1_MASK) != 0;
}
-#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
-#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
-#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask))
-#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1))
-#define RVC_X(X, s, mask) RV_X_mask(X, s, mask)
+#define INSN_MATCH_LB 0x3
+#define INSN_MASK_LB 0x707f
+#define INSN_MATCH_LH 0x1003
+#define INSN_MASK_LH 0x707f
+#define INSN_MATCH_LW 0x2003
+#define INSN_MASK_LW 0x707f
+#define INSN_MATCH_LD 0x3003
+#define INSN_MASK_LD 0x707f
+#define INSN_MATCH_LBU 0x4003
+#define INSN_MASK_LBU 0x707f
+#define INSN_MATCH_LHU 0x5003
+#define INSN_MASK_LHU 0x707f
+#define INSN_MATCH_LWU 0x6003
+#define INSN_MASK_LWU 0x707f
+#define INSN_MATCH_SB 0x23
+#define INSN_MASK_SB 0x707f
+#define INSN_MATCH_SH 0x1023
+#define INSN_MASK_SH 0x707f
+#define INSN_MATCH_SW 0x2023
+#define INSN_MASK_SW 0x707f
+#define INSN_MATCH_SD 0x3023
+#define INSN_MASK_SD 0x707f
+
+#define INSN_MATCH_C_LD 0x6000
+#define INSN_MASK_C_LD 0xe003
+#define INSN_MATCH_C_SD 0xe000
+#define INSN_MASK_C_SD 0xe003
+#define INSN_MATCH_C_LW 0x4000
+#define INSN_MASK_C_LW 0xe003
+#define INSN_MATCH_C_SW 0xc000
+#define INSN_MASK_C_SW 0xe003
+#define INSN_MATCH_C_LDSP 0x6002
+#define INSN_MASK_C_LDSP 0xe003
+#define INSN_MATCH_C_SDSP 0xe002
+#define INSN_MASK_C_SDSP 0xe003
+#define INSN_MATCH_C_LWSP 0x4002
+#define INSN_MASK_C_LWSP 0xe003
+#define INSN_MATCH_C_SWSP 0xc002
+#define INSN_MASK_C_SWSP 0xe003
+
+#define INSN_OPCODE_MASK 0x007c
+#define INSN_OPCODE_SHIFT 2
+#define INSN_OPCODE_SYSTEM 28
+
+#define INSN_MASK_WFI 0xffffffff
+#define INSN_MATCH_WFI 0x10500073
+
+#define INSN_MASK_WRS 0xffffffff
+#define INSN_MATCH_WRS 0x00d00073
+
+#define INSN_MATCH_CSRRW 0x1073
+#define INSN_MASK_CSRRW 0x707f
+#define INSN_MATCH_CSRRS 0x2073
+#define INSN_MASK_CSRRS 0x707f
+#define INSN_MATCH_CSRRC 0x3073
+#define INSN_MASK_CSRRC 0x707f
+#define INSN_MATCH_CSRRWI 0x5073
+#define INSN_MASK_CSRRWI 0x707f
+#define INSN_MATCH_CSRRSI 0x6073
+#define INSN_MASK_CSRRSI 0x707f
+#define INSN_MATCH_CSRRCI 0x7073
+#define INSN_MASK_CSRRCI 0x707f
+
+#define INSN_MATCH_FLW 0x2007
+#define INSN_MASK_FLW 0x707f
+#define INSN_MATCH_FLD 0x3007
+#define INSN_MASK_FLD 0x707f
+#define INSN_MATCH_FLQ 0x4007
+#define INSN_MASK_FLQ 0x707f
+#define INSN_MATCH_FSW 0x2027
+#define INSN_MASK_FSW 0x707f
+#define INSN_MATCH_FSD 0x3027
+#define INSN_MASK_FSD 0x707f
+#define INSN_MATCH_FSQ 0x4027
+#define INSN_MASK_FSQ 0x707f
+
+#define INSN_MATCH_C_FLD 0x2000
+#define INSN_MASK_C_FLD 0xe003
+#define INSN_MATCH_C_FLW 0x6000
+#define INSN_MASK_C_FLW 0xe003
+#define INSN_MATCH_C_FSD 0xa000
+#define INSN_MASK_C_FSD 0xe003
+#define INSN_MATCH_C_FSW 0xe000
+#define INSN_MASK_C_FSW 0xe003
+#define INSN_MATCH_C_FLDSP 0x2002
+#define INSN_MASK_C_FLDSP 0xe003
+#define INSN_MATCH_C_FSDSP 0xa002
+#define INSN_MASK_C_FSDSP 0xe003
+#define INSN_MATCH_C_FLWSP 0x6002
+#define INSN_MASK_C_FLWSP 0xe003
+#define INSN_MATCH_C_FSWSP 0xe002
+#define INSN_MASK_C_FSWSP 0xe003
+
+#define INSN_MATCH_C_LHU 0x8400
+#define INSN_MASK_C_LHU 0xfc43
+#define INSN_MATCH_C_LH 0x8440
+#define INSN_MASK_C_LH 0xfc43
+#define INSN_MATCH_C_SH 0x8c00
+#define INSN_MASK_C_SH 0xfc43
+
+#define INSN_16BIT_MASK 0x3
+#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
+#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
+
+#define SHIFT_RIGHT(x, y) \
+ ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
+
+#define REG_MASK \
+ ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
+
+#define REG_OFFSET(insn, pos) \
+ (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
+
+#define REG_PTR(insn, pos, regs) \
+ ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
+
+#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
+#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
+#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
+#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
+#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
+#define GET_SP(regs) (*REG_PTR(2, 0, regs))
+#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
+#define IMM_I(insn) ((s32)(insn) >> 20)
+#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
+ (s32)(((insn) >> 7) & 0x1f))
+
+#define SH_RD 7
+#define SH_RS1 15
+#define SH_RS2 20
+#define SH_RS2C 2
+#define MASK_RX 0x1f
+
+#if defined(CONFIG_64BIT)
+#define LOG_REGBYTES 3
+#else
+#define LOG_REGBYTES 2
+#endif
+
+#define MASK_FUNCT3 0x7000
+
+#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
+
+#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
+#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
+#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask))
+#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1))
+#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
+ (RV_X(x, 10, 3) << 3) | \
+ (RV_X(x, 5, 1) << 6))
+#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
+ (RV_X(x, 5, 2) << 6))
+#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
+ (RV_X(x, 12, 1) << 5) | \
+ (RV_X(x, 2, 2) << 6))
+#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
+ (RV_X(x, 12, 1) << 5) | \
+ (RV_X(x, 2, 3) << 6))
+#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
+ (RV_X(x, 7, 2) << 6))
+#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
+ (RV_X(x, 7, 3) << 6))
+#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
+#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
+#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
+#define RVC_X(X, s, mask) RV_X_mask(X, s, mask)
#define RV_EXTRACT_RS1_REG(x) \
({typeof(x) x_ = (x); \
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index ac8f479a3f9c..b52df35a5e05 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -19,148 +19,6 @@
#include <asm/vector.h>
#include <asm/insn.h>
-#define INSN_MATCH_LB 0x3
-#define INSN_MASK_LB 0x707f
-#define INSN_MATCH_LH 0x1003
-#define INSN_MASK_LH 0x707f
-#define INSN_MATCH_LW 0x2003
-#define INSN_MASK_LW 0x707f
-#define INSN_MATCH_LD 0x3003
-#define INSN_MASK_LD 0x707f
-#define INSN_MATCH_LBU 0x4003
-#define INSN_MASK_LBU 0x707f
-#define INSN_MATCH_LHU 0x5003
-#define INSN_MASK_LHU 0x707f
-#define INSN_MATCH_LWU 0x6003
-#define INSN_MASK_LWU 0x707f
-#define INSN_MATCH_SB 0x23
-#define INSN_MASK_SB 0x707f
-#define INSN_MATCH_SH 0x1023
-#define INSN_MASK_SH 0x707f
-#define INSN_MATCH_SW 0x2023
-#define INSN_MASK_SW 0x707f
-#define INSN_MATCH_SD 0x3023
-#define INSN_MASK_SD 0x707f
-
-#define INSN_MATCH_FLW 0x2007
-#define INSN_MASK_FLW 0x707f
-#define INSN_MATCH_FLD 0x3007
-#define INSN_MASK_FLD 0x707f
-#define INSN_MATCH_FLQ 0x4007
-#define INSN_MASK_FLQ 0x707f
-#define INSN_MATCH_FSW 0x2027
-#define INSN_MASK_FSW 0x707f
-#define INSN_MATCH_FSD 0x3027
-#define INSN_MASK_FSD 0x707f
-#define INSN_MATCH_FSQ 0x4027
-#define INSN_MASK_FSQ 0x707f
-
-#define INSN_MATCH_C_LD 0x6000
-#define INSN_MASK_C_LD 0xe003
-#define INSN_MATCH_C_SD 0xe000
-#define INSN_MASK_C_SD 0xe003
-#define INSN_MATCH_C_LW 0x4000
-#define INSN_MASK_C_LW 0xe003
-#define INSN_MATCH_C_SW 0xc000
-#define INSN_MASK_C_SW 0xe003
-#define INSN_MATCH_C_LDSP 0x6002
-#define INSN_MASK_C_LDSP 0xe003
-#define INSN_MATCH_C_SDSP 0xe002
-#define INSN_MASK_C_SDSP 0xe003
-#define INSN_MATCH_C_LWSP 0x4002
-#define INSN_MASK_C_LWSP 0xe003
-#define INSN_MATCH_C_SWSP 0xc002
-#define INSN_MASK_C_SWSP 0xe003
-
-#define INSN_MATCH_C_FLD 0x2000
-#define INSN_MASK_C_FLD 0xe003
-#define INSN_MATCH_C_FLW 0x6000
-#define INSN_MASK_C_FLW 0xe003
-#define INSN_MATCH_C_FSD 0xa000
-#define INSN_MASK_C_FSD 0xe003
-#define INSN_MATCH_C_FSW 0xe000
-#define INSN_MASK_C_FSW 0xe003
-#define INSN_MATCH_C_FLDSP 0x2002
-#define INSN_MASK_C_FLDSP 0xe003
-#define INSN_MATCH_C_FSDSP 0xa002
-#define INSN_MASK_C_FSDSP 0xe003
-#define INSN_MATCH_C_FLWSP 0x6002
-#define INSN_MASK_C_FLWSP 0xe003
-#define INSN_MATCH_C_FSWSP 0xe002
-#define INSN_MASK_C_FSWSP 0xe003
-
-#define INSN_MATCH_C_LHU 0x8400
-#define INSN_MASK_C_LHU 0xfc43
-#define INSN_MATCH_C_LH 0x8440
-#define INSN_MASK_C_LH 0xfc43
-#define INSN_MATCH_C_SH 0x8c00
-#define INSN_MASK_C_SH 0xfc43
-
-#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
-
-#if defined(CONFIG_64BIT)
-#define LOG_REGBYTES 3
-#define XLEN 64
-#else
-#define LOG_REGBYTES 2
-#define XLEN 32
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-#define XLEN_MINUS_16 ((XLEN) - 16)
-
-#define SH_RD 7
-#define SH_RS1 15
-#define SH_RS2 20
-#define SH_RS2C 2
-
-#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
- (RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 1) << 6))
-#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 2) << 6))
-#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 2) << 6))
-#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 3) << 6))
-#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
- (RV_X(x, 7, 2) << 6))
-#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 7, 3) << 6))
-#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
-#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
-#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
-
-#define SHIFT_RIGHT(x, y) \
- ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
-
-#define REG_MASK \
- ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
-
-#define REG_OFFSET(insn, pos) \
- (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
-
-#define REG_PTR(insn, pos, regs) \
- (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
-
-#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
-#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
-#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
-#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
-#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
-#define GET_SP(regs) (*REG_PTR(2, 0, regs))
-#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
-#define IMM_I(insn) ((s32)(insn) >> 20)
-#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
- (s32)(((insn) >> 7) & 0x1f))
-#define MASK_FUNCT3 0x7000
-
-#define GET_PRECISION(insn) (((insn) >> 25) & 3)
-#define GET_RM(insn) (((insn) >> 12) & 7)
-#define PRECISION_S 0
-#define PRECISION_D 1
-
#ifdef CONFIG_FPU
#define FP_GET_RD(insn) (insn >> 7 & 0x1F)
diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c
index 62cb2ab4b636..de1f96ea6225 100644
--- a/arch/riscv/kvm/vcpu_insn.c
+++ b/arch/riscv/kvm/vcpu_insn.c
@@ -10,132 +10,6 @@
#include <asm/cpufeature.h>
#include <asm/insn.h>
-#define INSN_OPCODE_MASK 0x007c
-#define INSN_OPCODE_SHIFT 2
-#define INSN_OPCODE_SYSTEM 28
-
-#define INSN_MASK_WFI 0xffffffff
-#define INSN_MATCH_WFI 0x10500073
-
-#define INSN_MASK_WRS 0xffffffff
-#define INSN_MATCH_WRS 0x00d00073
-
-#define INSN_MATCH_CSRRW 0x1073
-#define INSN_MASK_CSRRW 0x707f
-#define INSN_MATCH_CSRRS 0x2073
-#define INSN_MASK_CSRRS 0x707f
-#define INSN_MATCH_CSRRC 0x3073
-#define INSN_MASK_CSRRC 0x707f
-#define INSN_MATCH_CSRRWI 0x5073
-#define INSN_MASK_CSRRWI 0x707f
-#define INSN_MATCH_CSRRSI 0x6073
-#define INSN_MASK_CSRRSI 0x707f
-#define INSN_MATCH_CSRRCI 0x7073
-#define INSN_MASK_CSRRCI 0x707f
-
-#define INSN_MATCH_LB 0x3
-#define INSN_MASK_LB 0x707f
-#define INSN_MATCH_LH 0x1003
-#define INSN_MASK_LH 0x707f
-#define INSN_MATCH_LW 0x2003
-#define INSN_MASK_LW 0x707f
-#define INSN_MATCH_LD 0x3003
-#define INSN_MASK_LD 0x707f
-#define INSN_MATCH_LBU 0x4003
-#define INSN_MASK_LBU 0x707f
-#define INSN_MATCH_LHU 0x5003
-#define INSN_MASK_LHU 0x707f
-#define INSN_MATCH_LWU 0x6003
-#define INSN_MASK_LWU 0x707f
-#define INSN_MATCH_SB 0x23
-#define INSN_MASK_SB 0x707f
-#define INSN_MATCH_SH 0x1023
-#define INSN_MASK_SH 0x707f
-#define INSN_MATCH_SW 0x2023
-#define INSN_MASK_SW 0x707f
-#define INSN_MATCH_SD 0x3023
-#define INSN_MASK_SD 0x707f
-
-#define INSN_MATCH_C_LD 0x6000
-#define INSN_MASK_C_LD 0xe003
-#define INSN_MATCH_C_SD 0xe000
-#define INSN_MASK_C_SD 0xe003
-#define INSN_MATCH_C_LW 0x4000
-#define INSN_MASK_C_LW 0xe003
-#define INSN_MATCH_C_SW 0xc000
-#define INSN_MASK_C_SW 0xe003
-#define INSN_MATCH_C_LDSP 0x6002
-#define INSN_MASK_C_LDSP 0xe003
-#define INSN_MATCH_C_SDSP 0xe002
-#define INSN_MASK_C_SDSP 0xe003
-#define INSN_MATCH_C_LWSP 0x4002
-#define INSN_MASK_C_LWSP 0xe003
-#define INSN_MATCH_C_SWSP 0xc002
-#define INSN_MASK_C_SWSP 0xe003
-
-#define INSN_16BIT_MASK 0x3
-
-#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
-
-#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
-
-#ifdef CONFIG_64BIT
-#define LOG_REGBYTES 3
-#else
-#define LOG_REGBYTES 2
-#endif
-#define REGBYTES (1 << LOG_REGBYTES)
-
-#define SH_RD 7
-#define SH_RS1 15
-#define SH_RS2 20
-#define SH_RS2C 2
-#define MASK_RX 0x1f
-
-#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
- (RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 1) << 6))
-#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 5, 2) << 6))
-#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 2) << 6))
-#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
- (RV_X(x, 12, 1) << 5) | \
- (RV_X(x, 2, 3) << 6))
-#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
- (RV_X(x, 7, 2) << 6))
-#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
- (RV_X(x, 7, 3) << 6))
-#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
-#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
-#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
-
-#define SHIFT_RIGHT(x, y) \
- ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
-
-#define REG_MASK \
- ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
-
-#define REG_OFFSET(insn, pos) \
- (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
-
-#define REG_PTR(insn, pos, regs) \
- ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
-
-#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
-
-#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
-#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
-#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
-#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
-#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
-#define GET_SP(regs) (*REG_PTR(2, 0, regs))
-#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
-#define IMM_I(insn) ((s32)(insn) >> 20)
-#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
- (s32)(((insn) >> 7) & 0x1f))
-
struct insn_func {
unsigned long mask;
unsigned long match;
--
2.39.2
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH v4 2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X()
2025-05-16 14:08 ` [PATCH v4 2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X() Alexandre Ghiti
@ 2025-05-19 12:43 ` Clément Léger
0 siblings, 0 replies; 7+ messages in thread
From: Clément Léger @ 2025-05-19 12:43 UTC (permalink / raw)
To: Alexandre Ghiti, Paul Walmsley, Palmer Dabbelt, Alexandre Ghiti,
Anup Patel, Atish Patra, linux-riscv, linux-kernel, kvm,
kvm-riscv
Cc: Andrew Jones
On 16/05/2025 16:08, Alexandre Ghiti wrote:
> RV_X() macro is defined in two different ways which is error prone.
>
> So harmonize its first definition and add another macro RV_X_mask() for
> the second one.
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/include/asm/insn.h | 39 +++++++++++++-------------
> arch/riscv/kernel/machine_kexec_file.c | 2 +-
> arch/riscv/kernel/traps_misaligned.c | 2 +-
> arch/riscv/kvm/vcpu_insn.c | 2 +-
> 4 files changed, 23 insertions(+), 22 deletions(-)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index 2a589a58b291..ac3e606feca2 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -288,43 +288,44 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
>
> #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
> #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
> -#define RV_X(X, s, mask) (((X) >> (s)) & (mask))
> -#define RVC_X(X, s, mask) RV_X(X, s, mask)
> +#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask))
> +#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1))
> +#define RVC_X(X, s, mask) RV_X_mask(X, s, mask)
>
> #define RV_EXTRACT_RS1_REG(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
> + (RV_X_mask(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
>
> #define RV_EXTRACT_RD_REG(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
> + (RV_X_mask(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
>
> #define RV_EXTRACT_UTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
> + (RV_X_mask(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
>
> #define RV_EXTRACT_JTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
> - (RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
> - (RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
> + (RV_X_mask(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
> + (RV_X_mask(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
> + (RV_X_mask(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
> (RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
>
> #define RV_EXTRACT_ITYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
> + (RV_X_mask(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
> (RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
>
> #define RV_EXTRACT_BTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
> - (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
> - (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
> + (RV_X_mask(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
> + (RV_X_mask(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
> + (RV_X_mask(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
> (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
>
> #define RVC_EXTRACT_C2_RS1_REG(x) \
> ({typeof(x) x_ = (x); \
> - (RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
> + (RV_X_mask(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
>
> #define RVC_EXTRACT_JTYPE_IMM(x) \
> ({typeof(x) x_ = (x); \
> @@ -346,10 +347,10 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
> (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
>
> #define RVG_EXTRACT_SYSTEM_CSR(x) \
> - ({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
> + ({typeof(x) x_ = (x); RV_X_mask(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
>
> #define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \
> - ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
> + ({typeof(x) x_ = (x); RV_X_mask(x_, RVFDQ_FL_FS_WIDTH_OFF, \
> RVFDQ_FL_FS_WIDTH_MASK); })
>
> #define RVV_EXTRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
> @@ -375,10 +376,10 @@ static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)
> {
> /* drop the old IMMs, all jal IMM bits sit at 31:12 */
> *insn &= ~GENMASK(31, 12);
> - *insn |= (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
> - (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
> - (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
> - (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
> + *insn |= (RV_X_mask(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
> + (RV_X_mask(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
> + (RV_X_mask(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
> + (RV_X_mask(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
> }
>
> /*
> diff --git a/arch/riscv/kernel/machine_kexec_file.c b/arch/riscv/kernel/machine_kexec_file.c
> index e36104af2e24..5c2ed4c396e9 100644
> --- a/arch/riscv/kernel/machine_kexec_file.c
> +++ b/arch/riscv/kernel/machine_kexec_file.c
> @@ -15,6 +15,7 @@
> #include <linux/memblock.h>
> #include <linux/vmalloc.h>
> #include <asm/setup.h>
> +#include <asm/insn.h>
>
> const struct kexec_file_ops * const kexec_file_loaders[] = {
> &elf_kexec_ops,
> @@ -109,7 +110,6 @@ static char *setup_kdump_cmdline(struct kimage *image, char *cmdline,
> }
> #endif
>
> -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
> #define RISCV_IMM_BITS 12
> #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
> #define RISCV_CONST_HIGH_PART(x) \
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index 77c788660223..ac8f479a3f9c 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -17,6 +17,7 @@
> #include <asm/hwprobe.h>
> #include <asm/cpufeature.h>
> #include <asm/vector.h>
> +#include <asm/insn.h>
>
> #define INSN_MATCH_LB 0x3
> #define INSN_MASK_LB 0x707f
> @@ -112,7 +113,6 @@
> #define SH_RS2 20
> #define SH_RS2C 2
>
> -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
> #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
> (RV_X(x, 10, 3) << 3) | \
> (RV_X(x, 5, 1) << 6))
> diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c
> index 97dec18e6989..62cb2ab4b636 100644
> --- a/arch/riscv/kvm/vcpu_insn.c
> +++ b/arch/riscv/kvm/vcpu_insn.c
> @@ -8,6 +8,7 @@
> #include <linux/kvm_host.h>
>
> #include <asm/cpufeature.h>
> +#include <asm/insn.h>
>
> #define INSN_OPCODE_MASK 0x007c
> #define INSN_OPCODE_SHIFT 2
> @@ -91,7 +92,6 @@
> #define SH_RS2C 2
> #define MASK_RX 0x1f
>
> -#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
> #define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
> (RV_X(x, 10, 3) << 3) | \
> (RV_X(x, 5, 1) << 6))
LGTM,
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Thanks,
Clément
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h
2025-05-16 14:08 ` [PATCH v4 3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h Alexandre Ghiti
@ 2025-05-19 12:44 ` Clément Léger
0 siblings, 0 replies; 7+ messages in thread
From: Clément Léger @ 2025-05-19 12:44 UTC (permalink / raw)
To: Alexandre Ghiti, Paul Walmsley, Palmer Dabbelt, Alexandre Ghiti,
Anup Patel, Atish Patra, linux-riscv, linux-kernel, kvm,
kvm-riscv
Cc: Andrew Jones
On 16/05/2025 16:08, Alexandre Ghiti wrote:
> kernel/traps_misaligned.c and kvm/vcpu_insn.c define the same macros to
> extract information from the instructions.
>
> Let's move the definitions into asm/insn.h to avoid this duplication.
>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/include/asm/insn.h | 171 ++++++++++++++++++++++++++-
> arch/riscv/kernel/traps_misaligned.c | 142 ----------------------
> arch/riscv/kvm/vcpu_insn.c | 126 --------------------
> 3 files changed, 166 insertions(+), 273 deletions(-)
>
> diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h
> index ac3e606feca2..ad26f859cfe5 100644
> --- a/arch/riscv/include/asm/insn.h
> +++ b/arch/riscv/include/asm/insn.h
> @@ -286,11 +286,172 @@ static __always_inline bool riscv_insn_is_c_jalr(u32 code)
> (code & RVC_INSN_J_RS1_MASK) != 0;
> }
>
> -#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
> -#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
> -#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask))
> -#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1))
> -#define RVC_X(X, s, mask) RV_X_mask(X, s, mask)
> +#define INSN_MATCH_LB 0x3
> +#define INSN_MASK_LB 0x707f
> +#define INSN_MATCH_LH 0x1003
> +#define INSN_MASK_LH 0x707f
> +#define INSN_MATCH_LW 0x2003
> +#define INSN_MASK_LW 0x707f
> +#define INSN_MATCH_LD 0x3003
> +#define INSN_MASK_LD 0x707f
> +#define INSN_MATCH_LBU 0x4003
> +#define INSN_MASK_LBU 0x707f
> +#define INSN_MATCH_LHU 0x5003
> +#define INSN_MASK_LHU 0x707f
> +#define INSN_MATCH_LWU 0x6003
> +#define INSN_MASK_LWU 0x707f
> +#define INSN_MATCH_SB 0x23
> +#define INSN_MASK_SB 0x707f
> +#define INSN_MATCH_SH 0x1023
> +#define INSN_MASK_SH 0x707f
> +#define INSN_MATCH_SW 0x2023
> +#define INSN_MASK_SW 0x707f
> +#define INSN_MATCH_SD 0x3023
> +#define INSN_MASK_SD 0x707f
> +
> +#define INSN_MATCH_C_LD 0x6000
> +#define INSN_MASK_C_LD 0xe003
> +#define INSN_MATCH_C_SD 0xe000
> +#define INSN_MASK_C_SD 0xe003
> +#define INSN_MATCH_C_LW 0x4000
> +#define INSN_MASK_C_LW 0xe003
> +#define INSN_MATCH_C_SW 0xc000
> +#define INSN_MASK_C_SW 0xe003
> +#define INSN_MATCH_C_LDSP 0x6002
> +#define INSN_MASK_C_LDSP 0xe003
> +#define INSN_MATCH_C_SDSP 0xe002
> +#define INSN_MASK_C_SDSP 0xe003
> +#define INSN_MATCH_C_LWSP 0x4002
> +#define INSN_MASK_C_LWSP 0xe003
> +#define INSN_MATCH_C_SWSP 0xc002
> +#define INSN_MASK_C_SWSP 0xe003
> +
> +#define INSN_OPCODE_MASK 0x007c
> +#define INSN_OPCODE_SHIFT 2
> +#define INSN_OPCODE_SYSTEM 28
> +
> +#define INSN_MASK_WFI 0xffffffff
> +#define INSN_MATCH_WFI 0x10500073
> +
> +#define INSN_MASK_WRS 0xffffffff
> +#define INSN_MATCH_WRS 0x00d00073
> +
> +#define INSN_MATCH_CSRRW 0x1073
> +#define INSN_MASK_CSRRW 0x707f
> +#define INSN_MATCH_CSRRS 0x2073
> +#define INSN_MASK_CSRRS 0x707f
> +#define INSN_MATCH_CSRRC 0x3073
> +#define INSN_MASK_CSRRC 0x707f
> +#define INSN_MATCH_CSRRWI 0x5073
> +#define INSN_MASK_CSRRWI 0x707f
> +#define INSN_MATCH_CSRRSI 0x6073
> +#define INSN_MASK_CSRRSI 0x707f
> +#define INSN_MATCH_CSRRCI 0x7073
> +#define INSN_MASK_CSRRCI 0x707f
> +
> +#define INSN_MATCH_FLW 0x2007
> +#define INSN_MASK_FLW 0x707f
> +#define INSN_MATCH_FLD 0x3007
> +#define INSN_MASK_FLD 0x707f
> +#define INSN_MATCH_FLQ 0x4007
> +#define INSN_MASK_FLQ 0x707f
> +#define INSN_MATCH_FSW 0x2027
> +#define INSN_MASK_FSW 0x707f
> +#define INSN_MATCH_FSD 0x3027
> +#define INSN_MASK_FSD 0x707f
> +#define INSN_MATCH_FSQ 0x4027
> +#define INSN_MASK_FSQ 0x707f
> +
> +#define INSN_MATCH_C_FLD 0x2000
> +#define INSN_MASK_C_FLD 0xe003
> +#define INSN_MATCH_C_FLW 0x6000
> +#define INSN_MASK_C_FLW 0xe003
> +#define INSN_MATCH_C_FSD 0xa000
> +#define INSN_MASK_C_FSD 0xe003
> +#define INSN_MATCH_C_FSW 0xe000
> +#define INSN_MASK_C_FSW 0xe003
> +#define INSN_MATCH_C_FLDSP 0x2002
> +#define INSN_MASK_C_FLDSP 0xe003
> +#define INSN_MATCH_C_FSDSP 0xa002
> +#define INSN_MASK_C_FSDSP 0xe003
> +#define INSN_MATCH_C_FLWSP 0x6002
> +#define INSN_MASK_C_FLWSP 0xe003
> +#define INSN_MATCH_C_FSWSP 0xe002
> +#define INSN_MASK_C_FSWSP 0xe003
> +
> +#define INSN_MATCH_C_LHU 0x8400
> +#define INSN_MASK_C_LHU 0xfc43
> +#define INSN_MATCH_C_LH 0x8440
> +#define INSN_MASK_C_LH 0xfc43
> +#define INSN_MATCH_C_SH 0x8c00
> +#define INSN_MASK_C_SH 0xfc43
> +
> +#define INSN_16BIT_MASK 0x3
> +#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
> +#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
> +
> +#define SHIFT_RIGHT(x, y) \
> + ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
> +
> +#define REG_MASK \
> + ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
> +
> +#define REG_OFFSET(insn, pos) \
> + (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
> +
> +#define REG_PTR(insn, pos, regs) \
> + ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
> +
> +#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
> +#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
> +#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
> +#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
> +#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
> +#define GET_SP(regs) (*REG_PTR(2, 0, regs))
> +#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
> +#define IMM_I(insn) ((s32)(insn) >> 20)
> +#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
> + (s32)(((insn) >> 7) & 0x1f))
> +
> +#define SH_RD 7
> +#define SH_RS1 15
> +#define SH_RS2 20
> +#define SH_RS2C 2
> +#define MASK_RX 0x1f
> +
> +#if defined(CONFIG_64BIT)
> +#define LOG_REGBYTES 3
> +#else
> +#define LOG_REGBYTES 2
> +#endif
> +
> +#define MASK_FUNCT3 0x7000
> +
> +#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
> +
> +#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
> +#define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
> +#define RV_X_mask(X, s, mask) (((X) >> (s)) & (mask))
> +#define RV_X(X, s, n) RV_X_mask(X, s, ((1 << (n)) - 1))
> +#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
> + (RV_X(x, 10, 3) << 3) | \
> + (RV_X(x, 5, 1) << 6))
> +#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
> + (RV_X(x, 5, 2) << 6))
> +#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
> + (RV_X(x, 12, 1) << 5) | \
> + (RV_X(x, 2, 2) << 6))
> +#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
> + (RV_X(x, 12, 1) << 5) | \
> + (RV_X(x, 2, 3) << 6))
> +#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
> + (RV_X(x, 7, 2) << 6))
> +#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
> + (RV_X(x, 7, 3) << 6))
> +#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
> +#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
> +#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
> +#define RVC_X(X, s, mask) RV_X_mask(X, s, mask)
>
> #define RV_EXTRACT_RS1_REG(x) \
> ({typeof(x) x_ = (x); \
> diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
> index ac8f479a3f9c..b52df35a5e05 100644
> --- a/arch/riscv/kernel/traps_misaligned.c
> +++ b/arch/riscv/kernel/traps_misaligned.c
> @@ -19,148 +19,6 @@
> #include <asm/vector.h>
> #include <asm/insn.h>
>
> -#define INSN_MATCH_LB 0x3
> -#define INSN_MASK_LB 0x707f
> -#define INSN_MATCH_LH 0x1003
> -#define INSN_MASK_LH 0x707f
> -#define INSN_MATCH_LW 0x2003
> -#define INSN_MASK_LW 0x707f
> -#define INSN_MATCH_LD 0x3003
> -#define INSN_MASK_LD 0x707f
> -#define INSN_MATCH_LBU 0x4003
> -#define INSN_MASK_LBU 0x707f
> -#define INSN_MATCH_LHU 0x5003
> -#define INSN_MASK_LHU 0x707f
> -#define INSN_MATCH_LWU 0x6003
> -#define INSN_MASK_LWU 0x707f
> -#define INSN_MATCH_SB 0x23
> -#define INSN_MASK_SB 0x707f
> -#define INSN_MATCH_SH 0x1023
> -#define INSN_MASK_SH 0x707f
> -#define INSN_MATCH_SW 0x2023
> -#define INSN_MASK_SW 0x707f
> -#define INSN_MATCH_SD 0x3023
> -#define INSN_MASK_SD 0x707f
> -
> -#define INSN_MATCH_FLW 0x2007
> -#define INSN_MASK_FLW 0x707f
> -#define INSN_MATCH_FLD 0x3007
> -#define INSN_MASK_FLD 0x707f
> -#define INSN_MATCH_FLQ 0x4007
> -#define INSN_MASK_FLQ 0x707f
> -#define INSN_MATCH_FSW 0x2027
> -#define INSN_MASK_FSW 0x707f
> -#define INSN_MATCH_FSD 0x3027
> -#define INSN_MASK_FSD 0x707f
> -#define INSN_MATCH_FSQ 0x4027
> -#define INSN_MASK_FSQ 0x707f
> -
> -#define INSN_MATCH_C_LD 0x6000
> -#define INSN_MASK_C_LD 0xe003
> -#define INSN_MATCH_C_SD 0xe000
> -#define INSN_MASK_C_SD 0xe003
> -#define INSN_MATCH_C_LW 0x4000
> -#define INSN_MASK_C_LW 0xe003
> -#define INSN_MATCH_C_SW 0xc000
> -#define INSN_MASK_C_SW 0xe003
> -#define INSN_MATCH_C_LDSP 0x6002
> -#define INSN_MASK_C_LDSP 0xe003
> -#define INSN_MATCH_C_SDSP 0xe002
> -#define INSN_MASK_C_SDSP 0xe003
> -#define INSN_MATCH_C_LWSP 0x4002
> -#define INSN_MASK_C_LWSP 0xe003
> -#define INSN_MATCH_C_SWSP 0xc002
> -#define INSN_MASK_C_SWSP 0xe003
> -
> -#define INSN_MATCH_C_FLD 0x2000
> -#define INSN_MASK_C_FLD 0xe003
> -#define INSN_MATCH_C_FLW 0x6000
> -#define INSN_MASK_C_FLW 0xe003
> -#define INSN_MATCH_C_FSD 0xa000
> -#define INSN_MASK_C_FSD 0xe003
> -#define INSN_MATCH_C_FSW 0xe000
> -#define INSN_MASK_C_FSW 0xe003
> -#define INSN_MATCH_C_FLDSP 0x2002
> -#define INSN_MASK_C_FLDSP 0xe003
> -#define INSN_MATCH_C_FSDSP 0xa002
> -#define INSN_MASK_C_FSDSP 0xe003
> -#define INSN_MATCH_C_FLWSP 0x6002
> -#define INSN_MASK_C_FLWSP 0xe003
> -#define INSN_MATCH_C_FSWSP 0xe002
> -#define INSN_MASK_C_FSWSP 0xe003
> -
> -#define INSN_MATCH_C_LHU 0x8400
> -#define INSN_MASK_C_LHU 0xfc43
> -#define INSN_MATCH_C_LH 0x8440
> -#define INSN_MASK_C_LH 0xfc43
> -#define INSN_MATCH_C_SH 0x8c00
> -#define INSN_MASK_C_SH 0xfc43
> -
> -#define INSN_LEN(insn) ((((insn) & 0x3) < 0x3) ? 2 : 4)
> -
> -#if defined(CONFIG_64BIT)
> -#define LOG_REGBYTES 3
> -#define XLEN 64
> -#else
> -#define LOG_REGBYTES 2
> -#define XLEN 32
> -#endif
> -#define REGBYTES (1 << LOG_REGBYTES)
> -#define XLEN_MINUS_16 ((XLEN) - 16)
> -
> -#define SH_RD 7
> -#define SH_RS1 15
> -#define SH_RS2 20
> -#define SH_RS2C 2
> -
> -#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
> - (RV_X(x, 10, 3) << 3) | \
> - (RV_X(x, 5, 1) << 6))
> -#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
> - (RV_X(x, 5, 2) << 6))
> -#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
> - (RV_X(x, 12, 1) << 5) | \
> - (RV_X(x, 2, 2) << 6))
> -#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
> - (RV_X(x, 12, 1) << 5) | \
> - (RV_X(x, 2, 3) << 6))
> -#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
> - (RV_X(x, 7, 2) << 6))
> -#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
> - (RV_X(x, 7, 3) << 6))
> -#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
> -#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
> -#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
> -
> -#define SHIFT_RIGHT(x, y) \
> - ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
> -
> -#define REG_MASK \
> - ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
> -
> -#define REG_OFFSET(insn, pos) \
> - (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
> -
> -#define REG_PTR(insn, pos, regs) \
> - (ulong *)((ulong)(regs) + REG_OFFSET(insn, pos))
> -
> -#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
> -#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
> -#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
> -#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
> -#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
> -#define GET_SP(regs) (*REG_PTR(2, 0, regs))
> -#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
> -#define IMM_I(insn) ((s32)(insn) >> 20)
> -#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
> - (s32)(((insn) >> 7) & 0x1f))
> -#define MASK_FUNCT3 0x7000
> -
> -#define GET_PRECISION(insn) (((insn) >> 25) & 3)
> -#define GET_RM(insn) (((insn) >> 12) & 7)
> -#define PRECISION_S 0
> -#define PRECISION_D 1
> -
> #ifdef CONFIG_FPU
>
> #define FP_GET_RD(insn) (insn >> 7 & 0x1F)
> diff --git a/arch/riscv/kvm/vcpu_insn.c b/arch/riscv/kvm/vcpu_insn.c
> index 62cb2ab4b636..de1f96ea6225 100644
> --- a/arch/riscv/kvm/vcpu_insn.c
> +++ b/arch/riscv/kvm/vcpu_insn.c
> @@ -10,132 +10,6 @@
> #include <asm/cpufeature.h>
> #include <asm/insn.h>
>
> -#define INSN_OPCODE_MASK 0x007c
> -#define INSN_OPCODE_SHIFT 2
> -#define INSN_OPCODE_SYSTEM 28
> -
> -#define INSN_MASK_WFI 0xffffffff
> -#define INSN_MATCH_WFI 0x10500073
> -
> -#define INSN_MASK_WRS 0xffffffff
> -#define INSN_MATCH_WRS 0x00d00073
> -
> -#define INSN_MATCH_CSRRW 0x1073
> -#define INSN_MASK_CSRRW 0x707f
> -#define INSN_MATCH_CSRRS 0x2073
> -#define INSN_MASK_CSRRS 0x707f
> -#define INSN_MATCH_CSRRC 0x3073
> -#define INSN_MASK_CSRRC 0x707f
> -#define INSN_MATCH_CSRRWI 0x5073
> -#define INSN_MASK_CSRRWI 0x707f
> -#define INSN_MATCH_CSRRSI 0x6073
> -#define INSN_MASK_CSRRSI 0x707f
> -#define INSN_MATCH_CSRRCI 0x7073
> -#define INSN_MASK_CSRRCI 0x707f
> -
> -#define INSN_MATCH_LB 0x3
> -#define INSN_MASK_LB 0x707f
> -#define INSN_MATCH_LH 0x1003
> -#define INSN_MASK_LH 0x707f
> -#define INSN_MATCH_LW 0x2003
> -#define INSN_MASK_LW 0x707f
> -#define INSN_MATCH_LD 0x3003
> -#define INSN_MASK_LD 0x707f
> -#define INSN_MATCH_LBU 0x4003
> -#define INSN_MASK_LBU 0x707f
> -#define INSN_MATCH_LHU 0x5003
> -#define INSN_MASK_LHU 0x707f
> -#define INSN_MATCH_LWU 0x6003
> -#define INSN_MASK_LWU 0x707f
> -#define INSN_MATCH_SB 0x23
> -#define INSN_MASK_SB 0x707f
> -#define INSN_MATCH_SH 0x1023
> -#define INSN_MASK_SH 0x707f
> -#define INSN_MATCH_SW 0x2023
> -#define INSN_MASK_SW 0x707f
> -#define INSN_MATCH_SD 0x3023
> -#define INSN_MASK_SD 0x707f
> -
> -#define INSN_MATCH_C_LD 0x6000
> -#define INSN_MASK_C_LD 0xe003
> -#define INSN_MATCH_C_SD 0xe000
> -#define INSN_MASK_C_SD 0xe003
> -#define INSN_MATCH_C_LW 0x4000
> -#define INSN_MASK_C_LW 0xe003
> -#define INSN_MATCH_C_SW 0xc000
> -#define INSN_MASK_C_SW 0xe003
> -#define INSN_MATCH_C_LDSP 0x6002
> -#define INSN_MASK_C_LDSP 0xe003
> -#define INSN_MATCH_C_SDSP 0xe002
> -#define INSN_MASK_C_SDSP 0xe003
> -#define INSN_MATCH_C_LWSP 0x4002
> -#define INSN_MASK_C_LWSP 0xe003
> -#define INSN_MATCH_C_SWSP 0xc002
> -#define INSN_MASK_C_SWSP 0xe003
> -
> -#define INSN_16BIT_MASK 0x3
> -
> -#define INSN_IS_16BIT(insn) (((insn) & INSN_16BIT_MASK) != INSN_16BIT_MASK)
> -
> -#define INSN_LEN(insn) (INSN_IS_16BIT(insn) ? 2 : 4)
> -
> -#ifdef CONFIG_64BIT
> -#define LOG_REGBYTES 3
> -#else
> -#define LOG_REGBYTES 2
> -#endif
> -#define REGBYTES (1 << LOG_REGBYTES)
> -
> -#define SH_RD 7
> -#define SH_RS1 15
> -#define SH_RS2 20
> -#define SH_RS2C 2
> -#define MASK_RX 0x1f
> -
> -#define RVC_LW_IMM(x) ((RV_X(x, 6, 1) << 2) | \
> - (RV_X(x, 10, 3) << 3) | \
> - (RV_X(x, 5, 1) << 6))
> -#define RVC_LD_IMM(x) ((RV_X(x, 10, 3) << 3) | \
> - (RV_X(x, 5, 2) << 6))
> -#define RVC_LWSP_IMM(x) ((RV_X(x, 4, 3) << 2) | \
> - (RV_X(x, 12, 1) << 5) | \
> - (RV_X(x, 2, 2) << 6))
> -#define RVC_LDSP_IMM(x) ((RV_X(x, 5, 2) << 3) | \
> - (RV_X(x, 12, 1) << 5) | \
> - (RV_X(x, 2, 3) << 6))
> -#define RVC_SWSP_IMM(x) ((RV_X(x, 9, 4) << 2) | \
> - (RV_X(x, 7, 2) << 6))
> -#define RVC_SDSP_IMM(x) ((RV_X(x, 10, 3) << 3) | \
> - (RV_X(x, 7, 3) << 6))
> -#define RVC_RS1S(insn) (8 + RV_X(insn, SH_RD, 3))
> -#define RVC_RS2S(insn) (8 + RV_X(insn, SH_RS2C, 3))
> -#define RVC_RS2(insn) RV_X(insn, SH_RS2C, 5)
> -
> -#define SHIFT_RIGHT(x, y) \
> - ((y) < 0 ? ((x) << -(y)) : ((x) >> (y)))
> -
> -#define REG_MASK \
> - ((1 << (5 + LOG_REGBYTES)) - (1 << LOG_REGBYTES))
> -
> -#define REG_OFFSET(insn, pos) \
> - (SHIFT_RIGHT((insn), (pos) - LOG_REGBYTES) & REG_MASK)
> -
> -#define REG_PTR(insn, pos, regs) \
> - ((ulong *)((ulong)(regs) + REG_OFFSET(insn, pos)))
> -
> -#define GET_FUNCT3(insn) (((insn) >> 12) & 7)
> -
> -#define GET_RS1(insn, regs) (*REG_PTR(insn, SH_RS1, regs))
> -#define GET_RS2(insn, regs) (*REG_PTR(insn, SH_RS2, regs))
> -#define GET_RS1S(insn, regs) (*REG_PTR(RVC_RS1S(insn), 0, regs))
> -#define GET_RS2S(insn, regs) (*REG_PTR(RVC_RS2S(insn), 0, regs))
> -#define GET_RS2C(insn, regs) (*REG_PTR(insn, SH_RS2C, regs))
> -#define GET_SP(regs) (*REG_PTR(2, 0, regs))
> -#define SET_RD(insn, regs, val) (*REG_PTR(insn, SH_RD, regs) = (val))
> -#define IMM_I(insn) ((s32)(insn) >> 20)
> -#define IMM_S(insn) (((s32)(insn) >> 25 << 5) | \
> - (s32)(((insn) >> 7) & 0x1f))
> -
> struct insn_func {
> unsigned long mask;
> unsigned long match;
LGTM,
Reviewed-by: Clément Léger <cleger@rivosinc.com>
Thanks,
Clément
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH v4 0/3] Move duplicated instructions macros into asm/insn.h
2025-05-16 14:08 [PATCH v4 0/3] Move duplicated instructions macros into asm/insn.h Alexandre Ghiti
` (2 preceding siblings ...)
2025-05-16 14:08 ` [PATCH v4 3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h Alexandre Ghiti
@ 2025-06-04 14:33 ` patchwork-bot+linux-riscv
3 siblings, 0 replies; 7+ messages in thread
From: patchwork-bot+linux-riscv @ 2025-06-04 14:33 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: linux-riscv, paul.walmsley, palmer, alex, anup, atishp,
linux-kernel, kvm, kvm-riscv
Hello:
This series was applied to riscv/linux.git (for-next)
by Alexandre Ghiti <alexghiti@rivosinc.com>:
On Fri, 16 May 2025 16:08:02 +0200 you wrote:
> The instructions parsing macros were duplicated and one of them had different
> implementations, which is error prone.
>
> So let's consolidate those macros in asm/insn.h.
>
> v1: https://lore.kernel.org/linux-riscv/20250422082545.450453-1-alexghiti@rivosinc.com/
> v2: https://lore.kernel.org/linux-riscv/20250508082215.88658-1-alexghiti@rivosinc.com/
> v3: https://lore.kernel.org/linux-riscv/20250508125202.108613-1-alexghiti@rivosinc.com/
>
> [...]
Here is the summary with links:
- [v4,1/3] riscv: Fix typo EXRACT -> EXTRACT
https://git.kernel.org/riscv/c/00542578d2fd
- [v4,2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X()
https://git.kernel.org/riscv/c/9908f88a651e
- [v4,3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h
https://git.kernel.org/riscv/c/4f8d6dc47e46
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2025-06-04 14:32 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-16 14:08 [PATCH v4 0/3] Move duplicated instructions macros into asm/insn.h Alexandre Ghiti
2025-05-16 14:08 ` [PATCH v4 1/3] riscv: Fix typo EXRACT -> EXTRACT Alexandre Ghiti
2025-05-16 14:08 ` [PATCH v4 2/3] riscv: Strengthen duplicate and inconsistent definition of RV_X() Alexandre Ghiti
2025-05-19 12:43 ` Clément Léger
2025-05-16 14:08 ` [PATCH v4 3/3] riscv: Move all duplicate insn parsing macros into asm/insn.h Alexandre Ghiti
2025-05-19 12:44 ` Clément Léger
2025-06-04 14:33 ` [PATCH v4 0/3] Move duplicated instructions " patchwork-bot+linux-riscv
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