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Mon, 14 Jul 2025 22:16:25 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Saeed Mahameed , Leon Romanovsky , Tariq Toukan , Mark Bloch , "Richard Cochran" , , , , Carolina Jubran Subject: [PATCH net-next 0/3] Support exposing raw cycle counters in PTP and mlx5 Date: Tue, 15 Jul 2025 08:15:30 +0300 Message-ID: <1752556533-39218-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 8bit X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN1PEPF0000468E:EE_|CY1PR12MB9625:EE_ X-MS-Office365-Filtering-Correlation-Id: b9e6a229-28ee-47fd-43a9-08ddc35ecb2d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|7416014|376014|1800799024|82310400026; X-Microsoft-Antispam-Message-Info: =?utf-8?B?K1NLdHhrem5iRnhiWUtMRmVRSlc1MFNYRUVyVkNhRGt1ZUwxQTBKeUdhbGlJ?= =?utf-8?B?dFA2Vm8zTGova2VaSHlSenZWQ081dFQ4dXFKb2tPNmU5SGROR1dBc3ZNN29W?= =?utf-8?B?NTYrdDBUNFAvckZnaVZVbVQyL3kvMzlXRnRheXVST09nWHBNUVFOZWNwVnY4?= =?utf-8?B?VjFTbDZVNnF3R2N3QzNqQ2xOQTZiNm16elA0RHNuQ24yN2lvVUs0NEJVekh4?= =?utf-8?B?RTFnSVpPR1JNK2F2TUFuYytmL2ZueTc2dUhVWWNqK0tGSlozc1libmxiNjRN?= =?utf-8?B?TnhYaGEyM3M2d3cxMGRrWTQ4ZEUrdmJId0M3Nm5iNWUyZFl1K3ZQWmU5U1hk?= =?utf-8?B?VExRblZkQlpCdVVRWnh2UWorVkxwc0x4OUxuVmFHOHliL1pGRUhUbEV2V2ll?= =?utf-8?B?dW5zNGJpNlRaUVNyMnpFVDRLcVpDNmZuRFhhSGFINzRhVGtuY1hRODQ5WnND?= =?utf-8?B?THRRSFdtRUl4ZUFCUDhJNEREQkNvSzZSc2t1MDF6REtXT0ltT3pucDdEZHZi?= =?utf-8?B?YTZUZnN6NFQxYmI4ekpuSXpaLzc3YTlXUlNLUFFFYlFTcXd0NWZ6UnQ2bCtF?= =?utf-8?B?ckNscFdJNGtOdytlK3NtRkNocktNSHI0SGhZL1hlZ1ExZ1QrdW8xV2lzNTdl?= =?utf-8?B?YUYrdTIwNmdlZHYzZy9STDNsY3pzN200bFFKcmdSeW5NelBWS1YrSjd3QWwx?= =?utf-8?B?YUU0SzVHZFF5ZnpsUUNUbWErR01yek1wemJNTDFxMXF2SVFkUlVIdSt5NVQv?= =?utf-8?B?bjdnLzlMZEpPNm5MRVZRc0dWd3daT1RTbDJTL1hkUW0rWElndXo5WitvVlE2?= =?utf-8?B?R1pFdnNybG9YT3BHa0tpSXhJbENhWXhHOFd3RGVGTDdQMi9mUHdDaks5WFFS?= =?utf-8?B?YjhURmkzbXh4QkVuWjNqYnNhMlBBTjl3TGkzWjdRRVQ5SU94bjNDSHNQbGtN?= =?utf-8?B?MWRNclNzQ3V5WHhQQmtiNDFEaWszUlRqQWRpRklPN0lHVERVWUQvbUU0YXpB?= =?utf-8?B?TDhXZDdpT3NDOURuY29YWXovTnZ4Q2RNTGRiTEZrM0dRUjNZNFdYV2JiOUdr?= =?utf-8?B?UWVxM1V3SysvcVJ4Y0F2V2hEK1h3WmY5TGdDK2FYbGVOelhhZGpwS1hxaXMy?= =?utf-8?B?RDVZd0o5TzlCUVoyVFlsN3hPRGlQUGxmQ0xWaTF6RHNvT0hhaWJINjBVelZn?= =?utf-8?B?NEFPNXFDd1Fyb1EvVEVHNUlVMkVKUTdTeWdyM2p0S3MveElVZFc2OHNZRmZF?= =?utf-8?B?aGtSdVI3T2U2SzQwNXJyaUxJaU0wNloxbmNIMGYxZG15Z2RSeTB0ZVVqS1gy?= =?utf-8?B?Y1h5SUhTU0cwQ2k1RWtIbjZDdlloUXhKVHE1ZWFoWVlzQTlZeEN3YVlnVFhT?= =?utf-8?B?Um5id1VRNHpCa0hzUDc5Y284ODNzSGdPQnlHa0tLeUJZREtPU1RzRnltQzZl?= =?utf-8?B?ZlJSSld5MjdZaFdvM09aVHZ4Rm5OTk0yS1Q5a1E4ZHRqMEduMGljdVNzd0Nl?= =?utf-8?B?WmZXSmRIWEtqbk04U1BRWjcrNmVLcThxTkllRGtTK3Zydk9DU2ZSWFFid0tJ?= =?utf-8?B?MzZ6YUxTaEFKU2wvOTFlQnV4MEFqWGlOM1RlZFIyZHVzV1JZa2d4WnJHL2VE?= =?utf-8?B?ZVpSL0dYM3h2K3VyZEE3UzliaWwzZVF2ZGFqSHhxYlNmeURZR1JIZy9HdXFo?= =?utf-8?B?REp5WElxWE1rZWs3TnhOcWNra0dYdDBrU3Y2eGlzTXQzeTVOdDdoNDFoZ2tQ?= =?utf-8?B?eXBBVk95Q2ZrcGdCZkx5K2tXRGcwVnE5MGxEMlFETUF0Y0lScXRNRWF6eHly?= =?utf-8?B?eU03SlUrUVhxMjQ3UFY5M014c1RQRzdUVUhXV2tKOFZKZUU2aE1ocDV4Z3dQ?= =?utf-8?B?b3JYZmVNU0VUNENPeGkydUk1dmRwTXVCOTZ4a3pPZ2lvcHRyOUYxNHo4K3l4?= =?utf-8?B?Yy9xRHZLV21URklCQUlnNTlhUTN5WjdJbVhqT1VHYk5NWXJSSG1wdURJbllh?= =?utf-8?B?WkhpSDlyQ0dRTEd1K0ExWW40OHFCZUtxL1ZXb3p5a0FaUGFOc2pySlkzYlpW?= =?utf-8?Q?ld0Sdb?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(36860700013)(7416014)(376014)(1800799024)(82310400026);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Jul 2025 05:16:45.7600 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9e6a229-28ee-47fd-43a9-08ddc35ecb2d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN1PEPF0000468E.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9625 Hi, This series by Carolina adds support in ptp and usage in mlx5 for exposing the raw free-running cycle counter of PTP hardware clocks. Find detailed description by Carolina below [1]. Regards, Tariq [1] This patch series introduces support for exposing the raw free-running cycle counter of PTP hardware clocks. Some telemetry and low-level logging use cycle counter timestamps rather than nanoseconds. Currently, there is no generic interface to correlate these raw values with system time. To address this, the series introduces two new ioctl commands that allow userspace to query the device's raw cycle counter together with host time: - PTP_SYS_OFFSET_PRECISE_CYCLES - PTP_SYS_OFFSET_EXTENDED_CYCLES These commands work like their existing counterparts but return the device timestamp in cycle units instead of real-time nanoseconds. This can also be useful in the XDP fast path: if a driver inserts the raw cycle value into metadata instead of a real-time timestamp, it can avoid the overhead of converting cycles to time in the kernel. Then userspace can resolve the cycle-to-time mapping using this ioctl when needed. Adds the new PTP ioctls and integrates support in ptp_ioctl(): - ptp: Add ioctl commands to expose raw cycle counter values Support for exposing raw cycles in mlx5: - net/mlx5: Extract MTCTR register read logic into helper function - net/mlx5: Support getcyclesx and getcrosscycles Carolina Jubran (3): ptp: Add ioctl commands to expose raw cycle counter values net/mlx5: Extract MTCTR register read logic into helper function net/mlx5: Support getcyclesx and getcrosscycles .../ethernet/mellanox/mlx5/core/lib/clock.c | 113 ++++++++++++++++-- drivers/ptp/ptp_chardev.c | 34 ++++-- include/uapi/linux/ptp_clock.h | 4 + 3 files changed, 130 insertions(+), 21 deletions(-) base-commit: 06baf9bfa6ca8db7d5f32e12e27d1dc1b7cb3a8a -- 2.31.1