[PATCH v2 0/4] arm64: dts: socfpga: enable ethernet support for Agilex5

[PATCH v2 0/4] arm64: dts: socfpga: enable ethernet support for Agilex5

[Matthew Gerlach]

This patch set enables ethernet support for the Agilex5 family of SOCFPGAs,
and specifically enables gmac2 on the Agilex5 SOCFPGA Premium Development
Kit.

Patch 1 defines Agilex5 compatibility string in the device tree bindings.

Patch 2 defines the base gmac nodes it the Agilex5 DTSI.

Patch 3 enables gmac2 on the Agilex5 SOCFPGA Premium Development Kit.

Patch 4 add the new compatibility string to dwmac-socfpga.c.

Matthew Gerlach (2):
  dt-bindings: net: altr,socfpga-stmmac: Add compatible string for
    Agilex5
  arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit

Mun Yew Tham (2):
  arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5
  net: stmmac: dwmac-socfpga: Add xgmac support for Agilex5

 .../bindings/net/altr,socfpga-stmmac.yaml     |   8 +-
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  |  20 ++
 .../ethernet/stmicro/stmmac/dwmac-socfpga.c   |   1 +
 4 files changed, 363 insertions(+), 2 deletions(-)

-- 
2.35.3

[PATCH v2 1/4] dt-bindings: net: altr,socfpga-stmmac: Add compatible string for Agilex5

[Matthew Gerlach]

Add compatible string for the Altera Agilex5 variant of the Synopsys DWC
XGMAC IP version 2.10.

Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v2:
 - Remove generic compatible string for Agilex5.
---
 .../devicetree/bindings/net/altr,socfpga-stmmac.yaml      | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
index ec34daff2aa0..3a22d35db778 100644
--- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
+++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
@@ -11,8 +11,8 @@ maintainers:
 
 description:
   This binding describes the Altera SOCFPGA SoC implementation of the
-  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, and Agilex7 families
-  of chips.
+  Synopsys DWMAC for the Cyclone5, Arria5, Stratix10, Agilex5 and Agilex7
+  families of chips.
   # TODO: Determine how to handle the Arria10 reset-name, stmmaceth-ocp, that
   # does not validate against net/snps,dwmac.yaml.
 
@@ -23,6 +23,7 @@ select:
         enum:
           - altr,socfpga-stmmac
           - altr,socfpga-stmmac-a10-s10
+          - altr,socfpga-stmmac-agilex5
 
   required:
     - compatible
@@ -42,6 +43,9 @@ properties:
           - const: altr,socfpga-stmmac-a10-s10
           - const: snps,dwmac-3.74a
           - const: snps,dwmac
+      - items:
+          - const: altr,socfpga-stmmac-agilex5
+          - const: snps,dwxgmac-2.10
 
   clocks:
     minItems: 1
-- 
2.35.3

[PATCH v2 2/4] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5

[Matthew Gerlach]

From: Mun Yew Tham <mun.yew.tham@altera.com>

Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI
for the Agilex5 SOCFPGA.  Agilex5 has three Ethernet controllers based on
Synopsys DWC XGMAC IP version 2.10.

Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v2:
 - Remove generic compatible string for Agilex5.
---
 .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++
 1 file changed, 336 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
index 7d9394a04302..04e99cd7e74b 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
@@ -486,5 +486,341 @@ qspi: spi@108d2000 {
 			clocks = <&qspi_clk>;
 			status = "disabled";
 		};
+
+		gmac0: ethernet@10810000 {
+			compatible = "altr,socfpga-stmmac-agilex5",
+				     "snps,dwxgmac-2.10";
+			reg = <0x10810000 0x3500>;
+			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
+			reset-names = "stmmaceth", "ahb";
+			clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
+				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+			clock-names = "stmmaceth", "ptp_ref";
+			mac-address = [00 00 00 00 00 00];
+			tx-fifo-depth = <32768>;
+			rx-fifo-depth = <16384>;
+			snps,multicast-filter-bins = <64>;
+			snps,perfect-filter-entries = <64>;
+			snps,axi-config = <&stmmac_axi_emac0_setup>;
+			snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
+			snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
+			snps,pbl = <32>;
+			snps,tso;
+			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
+			snps,clk-csr = <0>;
+			status = "disabled";
+
+			stmmac_axi_emac0_setup: stmmac-axi-config {
+				snps,wr_osr_lmt = <31>;
+				snps,rd_osr_lmt = <31>;
+				snps,blen = <0 0 0 32 16 8 4>;
+			};
+
+			mtl_rx_emac0_setup: rx-queues-config {
+				snps,rx-queues-to-use = <8>;
+				snps,rx-sched-sp;
+				queue0 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+				};
+				queue1 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x1>;
+				};
+				queue2 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x2>;
+				};
+				queue3 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x3>;
+				};
+				queue4 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x4>;
+				};
+				queue5 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x5>;
+				};
+				queue6 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x6>;
+				};
+				queue7 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x7>;
+				};
+			};
+
+			mtl_tx_emac0_setup: tx-queues-config {
+				snps,tx-queues-to-use = <8>;
+				snps,tx-sched-wrr;
+				queue0 {
+					snps,weight = <0x09>;
+					snps,dcb-algorithm;
+				};
+				queue1 {
+					snps,weight = <0x0A>;
+					snps,dcb-algorithm;
+				};
+				queue2 {
+					snps,weight = <0x0B>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue3 {
+					snps,weight = <0x0C>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue4 {
+					snps,weight = <0x0D>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue5 {
+					snps,weight = <0x0E>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue6 {
+					snps,weight = <0x0F>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue7 {
+					snps,weight = <0x10>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+			};
+		};
+
+		gmac1: ethernet@10820000 {
+			compatible = "altr,socfpga-stmmac-agilex5",
+				     "snps,dwxgmac-2.10";
+			reg = <0x10820000 0x3500>;
+			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
+			reset-names = "stmmaceth", "ahb";
+			clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
+				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+			clock-names = "stmmaceth", "ptp_ref";
+			mac-address = [00 00 00 00 00 00];
+			tx-fifo-depth = <32768>;
+			rx-fifo-depth = <16384>;
+			snps,multicast-filter-bins = <64>;
+			snps,perfect-filter-entries = <64>;
+			snps,axi-config = <&stmmac_axi_emac1_setup>;
+			snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
+			snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
+			snps,pbl = <32>;
+			snps,tso;
+			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
+			snps,clk-csr = <0>;
+			status = "disabled";
+
+			stmmac_axi_emac1_setup: stmmac-axi-config {
+				snps,wr_osr_lmt = <31>;
+				snps,rd_osr_lmt = <31>;
+				snps,blen = <0 0 0 32 16 8 4>;
+			};
+
+			mtl_rx_emac1_setup: rx-queues-config {
+				snps,rx-queues-to-use = <8>;
+				snps,rx-sched-sp;
+				queue0 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+				};
+				queue1 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x1>;
+				};
+				queue2 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x2>;
+				};
+				queue3 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x3>;
+				};
+				queue4 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x4>;
+				};
+				queue5 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x5>;
+				};
+				queue6 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x6>;
+				};
+				queue7 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x7>;
+				};
+			};
+
+			mtl_tx_emac1_setup: tx-queues-config {
+				snps,tx-queues-to-use = <8>;
+				snps,tx-sched-wrr;
+				queue0 {
+					snps,weight = <0x09>;
+					snps,dcb-algorithm;
+				};
+				queue1 {
+					snps,weight = <0x0A>;
+					snps,dcb-algorithm;
+				};
+				queue2 {
+					snps,weight = <0x0B>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue3 {
+					snps,weight = <0x0C>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue4 {
+					snps,weight = <0x0D>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue5 {
+					snps,weight = <0x0E>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue6 {
+					snps,weight = <0x0F>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue7 {
+					snps,weight = <0x10>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+			};
+		};
+
+		gmac2: ethernet@10830000 {
+			compatible = "altr,socfpga-stmmac-agilex5",
+				     "snps,dwxgmac-2.10";
+			reg = <0x10830000 0x3500>;
+			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+			interrupt-names = "macirq";
+			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
+			reset-names = "stmmaceth", "ahb";
+			clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
+				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
+			clock-names = "stmmaceth", "ptp_ref";
+			mac-address = [00 00 00 00 00 00];
+			tx-fifo-depth = <32768>;
+			rx-fifo-depth = <16384>;
+			snps,multicast-filter-bins = <64>;
+			snps,perfect-filter-entries = <64>;
+			snps,axi-config = <&stmmac_axi_emac2_setup>;
+			snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
+			snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
+			snps,pbl = <32>;
+			snps,tso;
+			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
+			snps,clk-csr = <0>;
+			status = "disabled";
+
+			stmmac_axi_emac2_setup: stmmac-axi-config {
+				snps,wr_osr_lmt = <31>;
+				snps,rd_osr_lmt = <31>;
+				snps,blen = <0 0 0 32 16 8 4>;
+			};
+
+			mtl_rx_emac2_setup: rx-queues-config {
+				snps,rx-queues-to-use = <8>;
+				snps,rx-sched-sp;
+				queue0 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x0>;
+				};
+				queue1 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x1>;
+				};
+				queue2 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x2>;
+				};
+				queue3 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x3>;
+				};
+				queue4 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x4>;
+				};
+				queue5 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x5>;
+				};
+				queue6 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x6>;
+				};
+				queue7 {
+					snps,dcb-algorithm;
+					snps,map-to-dma-channel = <0x7>;
+				};
+			};
+
+			mtl_tx_emac2_setup: tx-queues-config {
+				snps,tx-queues-to-use = <8>;
+				snps,tx-sched-wrr;
+				queue0 {
+					snps,weight = <0x09>;
+					snps,dcb-algorithm;
+				};
+				queue1 {
+					snps,weight = <0x0A>;
+					snps,dcb-algorithm;
+				};
+				queue2 {
+					snps,weight = <0x0B>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue3 {
+					snps,weight = <0x0C>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue4 {
+					snps,weight = <0x0D>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue5 {
+					snps,weight = <0x0E>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue6 {
+					snps,weight = <0x0F>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+				queue7 {
+					snps,weight = <0x10>;
+					snps,coe-unsupported;
+					snps,dcb-algorithm;
+				};
+			};
+		};
 	};
 };
-- 
2.35.3

[PATCH v2 3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit

[Matthew Gerlach]

Enable gmac2 on the Agilex5 SOCFGPA Development Kit. The MAC is connected
to a RGMII PHY on a daughter card. There are no RGMII clock delays
implemented the on PCB.

Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
v2:
 - change phy-mode to "rgmii-id"
 - add newline before inner device tree nodes
---
 .../boot/dts/intel/socfpga_agilex5_socdk.dts  | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
index d3b913b7902c..e9776e1cdc9a 100644
--- a/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
+++ b/arch/arm64/boot/dts/intel/socfpga_agilex5_socdk.dts
@@ -10,6 +10,9 @@ / {
 
 	aliases {
 		serial0 = &uart0;
+		ethernet0 = &gmac0;
+		ethernet1 = &gmac1;
+		ethernet2 = &gmac2;
 	};
 
 	chosen {
@@ -37,6 +40,23 @@ &gpio0 {
 	status = "okay";
 };
 
+&gmac2 {
+	status = "okay";
+	phy-mode = "rgmii-id";
+	phy-handle = <&emac2_phy0>;
+	max-frame-size = <9000>;
+
+	mdio0 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "snps,dwmac-mdio";
+
+		emac2_phy0: ethernet-phy@0 {
+			reg = <0>;
+		};
+	};
+};
+
 &gpio1 {
 	status = "okay";
 };
-- 
2.35.3

[PATCH v2 4/4] net: stmmac: dwmac-socfpga: Add xgmac support for Agilex5

[Matthew Gerlach]

From: Mun Yew Tham <mun.yew.tham@altera.com>

Add support for Agilex5 compatible value.

Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 72b50f6d72f4..01dd0cf0923c 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -515,6 +515,7 @@ static const struct socfpga_dwmac_ops socfpga_gen10_ops = {
 static const struct of_device_id socfpga_dwmac_match[] = {
 	{ .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
 	{ .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
+	{ .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_gen10_ops },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
-- 
2.35.3

Re: [PATCH v2 1/4] dt-bindings: net: altr,socfpga-stmmac: Add compatible string for Agilex5

[Rob Herring (Arm)]

On Thu, 24 Jul 2025 08:40:48 -0700, Matthew Gerlach wrote:
> Add compatible string for the Altera Agilex5 variant of the Synopsys DWC
> XGMAC IP version 2.10.
> 
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
> v2:
>  - Remove generic compatible string for Agilex5.
> ---
>  .../devicetree/bindings/net/altr,socfpga-stmmac.yaml      | 8 ++++++--
>  1 file changed, 6 insertions(+), 2 deletions(-)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH v2 0/4] arm64: dts: socfpga: enable ethernet support for Agilex5

[patchwork-bot+netdevbpf]

Hello:

This series was applied to netdev/net-next.git (main)
by Jakub Kicinski <kuba@kernel.org>:

On Thu, 24 Jul 2025 08:40:47 -0700 you wrote:
> This patch set enables ethernet support for the Agilex5 family of SOCFPGAs,
> and specifically enables gmac2 on the Agilex5 SOCFPGA Premium Development
> Kit.
> 
> Patch 1 defines Agilex5 compatibility string in the device tree bindings.
> 
> Patch 2 defines the base gmac nodes it the Agilex5 DTSI.
> 
> [...]

Here is the summary with links:
  - [v2,1/4] dt-bindings: net: altr,socfpga-stmmac: Add compatible string for Agilex5
    https://git.kernel.org/netdev/net-next/c/92068a32f978
  - [v2,2/4] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5
    (no matching commit)
  - [v2,3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
    (no matching commit)
  - [v2,4/4] net: stmmac: dwmac-socfpga: Add xgmac support for Agilex5
    https://git.kernel.org/netdev/net-next/c/a5e290aab8fc

You are awesome, thank you!
-- 
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html

Re: [PATCH v2 2/4] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5

[Matthew Gerlach]

On 7/24/25 8:40 AM, Matthew Gerlach wrote:
> From: Mun Yew Tham <mun.yew.tham@altera.com>
>
> Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI
> for the Agilex5 SOCFPGA.  Agilex5 has three Ethernet controllers based on
> Synopsys DWC XGMAC IP version 2.10.
>
> Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
> Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> ---
> v2:
>   - Remove generic compatible string for Agilex5.
> ---
>   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++
>   1 file changed, 336 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> index 7d9394a04302..04e99cd7e74b 100644
> --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> @@ -486,5 +486,341 @@ qspi: spi@108d2000 {
>   			clocks = <&qspi_clk>;
>   			status = "disabled";
>   		};

Is there any feedback for this patch and the next one in the series, 
"[PATCH v2 3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the 
Agilex5 dev kit"?

Thanks,
Matthew Gerlach

> +
> +		gmac0: ethernet@10810000 {
> +			compatible = "altr,socfpga-stmmac-agilex5",
> +				     "snps,dwxgmac-2.10";
> +			reg = <0x10810000 0x3500>;
> +			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
> +			reset-names = "stmmaceth", "ahb";
> +			clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
> +				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
> +			clock-names = "stmmaceth", "ptp_ref";
> +			mac-address = [00 00 00 00 00 00];
> +			tx-fifo-depth = <32768>;
> +			rx-fifo-depth = <16384>;
> +			snps,multicast-filter-bins = <64>;
> +			snps,perfect-filter-entries = <64>;
> +			snps,axi-config = <&stmmac_axi_emac0_setup>;
> +			snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
> +			snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
> +			snps,pbl = <32>;
> +			snps,tso;
> +			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> +			snps,clk-csr = <0>;
> +			status = "disabled";
> +
> +			stmmac_axi_emac0_setup: stmmac-axi-config {
> +				snps,wr_osr_lmt = <31>;
> +				snps,rd_osr_lmt = <31>;
> +				snps,blen = <0 0 0 32 16 8 4>;
> +			};
> +
> +			mtl_rx_emac0_setup: rx-queues-config {
> +				snps,rx-queues-to-use = <8>;
> +				snps,rx-sched-sp;
> +				queue0 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x0>;
> +				};
> +				queue1 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x1>;
> +				};
> +				queue2 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x2>;
> +				};
> +				queue3 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x3>;
> +				};
> +				queue4 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x4>;
> +				};
> +				queue5 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x5>;
> +				};
> +				queue6 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x6>;
> +				};
> +				queue7 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x7>;
> +				};
> +			};
> +
> +			mtl_tx_emac0_setup: tx-queues-config {
> +				snps,tx-queues-to-use = <8>;
> +				snps,tx-sched-wrr;
> +				queue0 {
> +					snps,weight = <0x09>;
> +					snps,dcb-algorithm;
> +				};
> +				queue1 {
> +					snps,weight = <0x0A>;
> +					snps,dcb-algorithm;
> +				};
> +				queue2 {
> +					snps,weight = <0x0B>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue3 {
> +					snps,weight = <0x0C>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue4 {
> +					snps,weight = <0x0D>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue5 {
> +					snps,weight = <0x0E>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue6 {
> +					snps,weight = <0x0F>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue7 {
> +					snps,weight = <0x10>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +			};
> +		};
> +
> +		gmac1: ethernet@10820000 {
> +			compatible = "altr,socfpga-stmmac-agilex5",
> +				     "snps,dwxgmac-2.10";
> +			reg = <0x10820000 0x3500>;
> +			interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			resets = <&rst EMAC1_RESET>, <&rst EMAC1_OCP_RESET>;
> +			reset-names = "stmmaceth", "ahb";
> +			clocks = <&clkmgr AGILEX5_EMAC1_CLK>,
> +				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
> +			clock-names = "stmmaceth", "ptp_ref";
> +			mac-address = [00 00 00 00 00 00];
> +			tx-fifo-depth = <32768>;
> +			rx-fifo-depth = <16384>;
> +			snps,multicast-filter-bins = <64>;
> +			snps,perfect-filter-entries = <64>;
> +			snps,axi-config = <&stmmac_axi_emac1_setup>;
> +			snps,mtl-rx-config = <&mtl_rx_emac1_setup>;
> +			snps,mtl-tx-config = <&mtl_tx_emac1_setup>;
> +			snps,pbl = <32>;
> +			snps,tso;
> +			altr,sysmgr-syscon = <&sysmgr 0x48 0>;
> +			snps,clk-csr = <0>;
> +			status = "disabled";
> +
> +			stmmac_axi_emac1_setup: stmmac-axi-config {
> +				snps,wr_osr_lmt = <31>;
> +				snps,rd_osr_lmt = <31>;
> +				snps,blen = <0 0 0 32 16 8 4>;
> +			};
> +
> +			mtl_rx_emac1_setup: rx-queues-config {
> +				snps,rx-queues-to-use = <8>;
> +				snps,rx-sched-sp;
> +				queue0 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x0>;
> +				};
> +				queue1 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x1>;
> +				};
> +				queue2 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x2>;
> +				};
> +				queue3 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x3>;
> +				};
> +				queue4 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x4>;
> +				};
> +				queue5 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x5>;
> +				};
> +				queue6 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x6>;
> +				};
> +				queue7 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x7>;
> +				};
> +			};
> +
> +			mtl_tx_emac1_setup: tx-queues-config {
> +				snps,tx-queues-to-use = <8>;
> +				snps,tx-sched-wrr;
> +				queue0 {
> +					snps,weight = <0x09>;
> +					snps,dcb-algorithm;
> +				};
> +				queue1 {
> +					snps,weight = <0x0A>;
> +					snps,dcb-algorithm;
> +				};
> +				queue2 {
> +					snps,weight = <0x0B>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue3 {
> +					snps,weight = <0x0C>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue4 {
> +					snps,weight = <0x0D>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue5 {
> +					snps,weight = <0x0E>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue6 {
> +					snps,weight = <0x0F>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue7 {
> +					snps,weight = <0x10>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +			};
> +		};
> +
> +		gmac2: ethernet@10830000 {
> +			compatible = "altr,socfpga-stmmac-agilex5",
> +				     "snps,dwxgmac-2.10";
> +			reg = <0x10830000 0x3500>;
> +			interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> +			interrupt-names = "macirq";
> +			resets = <&rst EMAC2_RESET>, <&rst EMAC2_OCP_RESET>;
> +			reset-names = "stmmaceth", "ahb";
> +			clocks = <&clkmgr AGILEX5_EMAC2_CLK>,
> +				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
> +			clock-names = "stmmaceth", "ptp_ref";
> +			mac-address = [00 00 00 00 00 00];
> +			tx-fifo-depth = <32768>;
> +			rx-fifo-depth = <16384>;
> +			snps,multicast-filter-bins = <64>;
> +			snps,perfect-filter-entries = <64>;
> +			snps,axi-config = <&stmmac_axi_emac2_setup>;
> +			snps,mtl-rx-config = <&mtl_rx_emac2_setup>;
> +			snps,mtl-tx-config = <&mtl_tx_emac2_setup>;
> +			snps,pbl = <32>;
> +			snps,tso;
> +			altr,sysmgr-syscon = <&sysmgr 0x4c 0>;
> +			snps,clk-csr = <0>;
> +			status = "disabled";
> +
> +			stmmac_axi_emac2_setup: stmmac-axi-config {
> +				snps,wr_osr_lmt = <31>;
> +				snps,rd_osr_lmt = <31>;
> +				snps,blen = <0 0 0 32 16 8 4>;
> +			};
> +
> +			mtl_rx_emac2_setup: rx-queues-config {
> +				snps,rx-queues-to-use = <8>;
> +				snps,rx-sched-sp;
> +				queue0 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x0>;
> +				};
> +				queue1 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x1>;
> +				};
> +				queue2 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x2>;
> +				};
> +				queue3 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x3>;
> +				};
> +				queue4 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x4>;
> +				};
> +				queue5 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x5>;
> +				};
> +				queue6 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x6>;
> +				};
> +				queue7 {
> +					snps,dcb-algorithm;
> +					snps,map-to-dma-channel = <0x7>;
> +				};
> +			};
> +
> +			mtl_tx_emac2_setup: tx-queues-config {
> +				snps,tx-queues-to-use = <8>;
> +				snps,tx-sched-wrr;
> +				queue0 {
> +					snps,weight = <0x09>;
> +					snps,dcb-algorithm;
> +				};
> +				queue1 {
> +					snps,weight = <0x0A>;
> +					snps,dcb-algorithm;
> +				};
> +				queue2 {
> +					snps,weight = <0x0B>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue3 {
> +					snps,weight = <0x0C>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue4 {
> +					snps,weight = <0x0D>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue5 {
> +					snps,weight = <0x0E>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue6 {
> +					snps,weight = <0x0F>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +				queue7 {
> +					snps,weight = <0x10>;
> +					snps,coe-unsupported;
> +					snps,dcb-algorithm;
> +				};
> +			};
> +		};
>   	};
>   };

Re: [PATCH v2 2/4] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5

[Matthew Gerlach]

On 8/4/25 7:57 AM, Matthew Gerlach wrote:
>
> On 7/24/25 8:40 AM, Matthew Gerlach wrote:
> > From: Mun Yew Tham <mun.yew.tham@altera.com>
> >
> > Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI
> > for the Agilex5 SOCFPGA.  Agilex5 has three Ethernet controllers based on
> > Synopsys DWC XGMAC IP version 2.10.
> >
> > Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
> > ---
> > v2:
> >   - Remove generic compatible string for Agilex5.
> > ---
> >   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 ++++++++++++++++++
> >   1 file changed, 336 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> > index 7d9394a04302..04e99cd7e74b 100644
> > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
> > @@ -486,5 +486,341 @@ qspi: spi@108d2000 {
> >   			clocks = <&qspi_clk>;
> >   			status = "disabled";
> >   		};
>
> Is there any feedback for this patch and the next one in the series,
> "[PATCH v2 3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the
> Agilex5 dev kit"?
>
> Thanks,
> Matthew Gerlach

Just checking in again. Is there any feedback on this patch (v2 2/4) or 
the next patch (v2 3/4)?
https://lore.kernel.org/lkml/20250724154052.205706-1-matthew.gerlach@altera.com/T/#m2a5f9a3d22dfef094986fd8a421051f55667b427 

https://lore.kernel.org/lkml/20250724154052.205706-1-matthew.gerlach@altera.com/T/#m3e3d9774dbdb34d646b53c04c46ec49d32254544

Thanks,
Matthew Gerlach

> > +
> > +		gmac0: ethernet@10810000 {
> > +			compatible = "altr,socfpga-stmmac-agilex5",
> > +				     "snps,dwxgmac-2.10";
> > +			reg = <0x10810000 0x3500>;
> > +			interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> > +			interrupt-names = "macirq";
> > +			resets = <&rst EMAC0_RESET>, <&rst EMAC0_OCP_RESET>;
> > +			reset-names = "stmmaceth", "ahb";
> > +			clocks = <&clkmgr AGILEX5_EMAC0_CLK>,
> > +				 <&clkmgr AGILEX5_EMAC_PTP_CLK>;
> > +			clock-names = "stmmaceth", "ptp_ref";
> > +			mac-address = [00 00 00 00 00 00];
> > +			tx-fifo-depth = <32768>;
> > +			rx-fifo-depth = <16384>;
> > +			snps,multicast-filter-bins = <64>;
> > +			snps,perfect-filter-entries = <64>;
> > +			snps,axi-config = <&stmmac_axi_emac0_setup>;
> > +			snps,mtl-rx-config = <&mtl_rx_emac0_setup>;
> > +			snps,mtl-tx-config = <&mtl_tx_emac0_setup>;
> > +			snps,pbl = <32>;
> > +			snps,tso;
> > +			altr,sysmgr-syscon = <&sysmgr 0x44 0>;
> > +			snps,clk-csr = <0>;
> > +			status = "disabled";
> > +
> > +			stmmac_axi_emac0_setup: stmmac-axi-config {
> > +				snps,wr_osr_lmt = <31>;
> > +				snps,rd_osr_lmt = <31>;
> > +				snps,blen = <0 0 0 32 16 8 4>;
> > +			};
> > +
> > +			mtl_rx_emac0_setup: rx-queues-config {
> > +				snps,rx-queues-to-use = <8>;
> > +				snps,rx-sched-sp;
> > +				queue0 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x0>;
> > +				};
> > +				queue1 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x1>;
> > +				};
> > +				queue2 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x2>;
> > +				};
> > +				queue3 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x3>;
> > +				};
> > +				queue4 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x4>;
> > +				};
> > +				queue5 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x5>;
> > +				};
> > +				queue6 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x6>;
> > +				};
> > +				queue7 {
> > +					snps,dcb-algorithm;
> > +					snps,map-to-dma-channel = <0x7>;
> > +				};
> > +			};
> > +
> > +			mtl_tx_emac0_setup: tx-queues-config {
> > +				snps,tx-queues-to-use = <8>;
> > +				snps,tx-sched-wrr;
> > +				queue0 {
> > +					snps,weight = <0x09>;
> > +					snps,dcb-algorithm;
> > +				};
> > +				queue1 {
> > +					snps,weight = <0x0A>;
> > +					snps,dcb-algorithm;
> > +				};
> > +				queue2 {
> > +					snps,weight = <0x0B>;
> > +					snps,coe-unsupported;
> > +					snps,dcb-algorithm;
> > +				};
> > +				queue3 {
> > +					snps,weight = <0x0C>;
> > +					snps,coe-unsupported;
> > +					snps,dcb-algorithm;
> > +				};
> > +				queue4 {
> > +					snps,weight = <0x0D>;
> > +					snps,coe-unsupported;
> > +					snps,dcb-algorithm;
> > +				};
> > +				queue5 {
> > +					snps,weight = <0x0E>;
> > +					snps,coe-unsupported;
> > +					snps,dcb-algorithm;
> > +				};
> > +				queue6 {
> > +					snps,weight = <0x0F>;
> > +					snps,coe-unsupported;
> > +					snps,dcb-algorithm;
> > +				};
> > +				queue7 {
> > +					snps,weight = <0x10>;
> > +					snps,coe-unsupported;
> > +					snps,dcb-algorithm;
> > +				};
> > +			};
> > +		};
> > +
>

Re: [PATCH v2 2/4] arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5

[Dinh Nguyen]

On 8/11/25 10:40, Matthew Gerlach wrote:
>
>
> On 8/4/25 7:57 AM, Matthew Gerlach wrote:
>>
>> On 7/24/25 8:40 AM, Matthew Gerlach wrote:
>> > From: Mun Yew Tham <mun.yew.tham@altera.com>
>> >
>> > Add the base device tree nodes for gmac0, gmac1, and gmac2 to the DTSI
>> > for the Agilex5 SOCFPGA.  Agilex5 has three Ethernet controllers 
>> based on
>> > Synopsys DWC XGMAC IP version 2.10.
>> >
>> > Signed-off-by: Mun Yew Tham <mun.yew.tham@altera.com>
>> > Signed-off-by: Matthew Gerlach <matthew.gerlach@altera.com>
>> > ---
>> > v2:
>> >   - Remove generic compatible string for Agilex5.
>> > ---
>> >   .../arm64/boot/dts/intel/socfpga_agilex5.dtsi | 336 
>> ++++++++++++++++++
>> >   1 file changed, 336 insertions(+)
>> >
>> > diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi 
>> b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> > index 7d9394a04302..04e99cd7e74b 100644
>> > --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> > +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi
>> > @@ -486,5 +486,341 @@ qspi: spi@108d2000 {
>> >               clocks = <&qspi_clk>;
>> >               status = "disabled";
>> >           };
>>
>> Is there any feedback for this patch and the next one in the series,
>> "[PATCH v2 3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the
>> Agilex5 dev kit"?
>>
>> Thanks,
>> Matthew Gerlach
>
> Just checking in again. Is there any feedback on this patch (v2 2/4) 
> or the next patch (v2 3/4)?
> https://lore.kernel.org/lkml/20250724154052.205706-1-matthew.gerlach@altera.com/T/#m2a5f9a3d22dfef094986fd8a421051f55667b427 
>
> https://lore.kernel.org/lkml/20250724154052.205706-1-matthew.gerlach@altera.com/T/#m3e3d9774dbdb34d646b53c04c46ec49d32254544 
>
>

Applied!

Thanks,

Dinh