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Tue, 16 Sep 2025 07:12:03 -0700 From: Tariq Toukan To: Eric Dumazet , Jakub Kicinski , Paolo Abeni , Andrew Lunn , "David S. Miller" CC: Jiri Pirko , Jonathan Corbet , "Leon Romanovsky" , Jason Gunthorpe , Saeed Mahameed , Tariq Toukan , Mark Bloch , Alexei Starovoitov , Daniel Borkmann , Jesper Dangaard Brouer , "John Fastabend" , , , , , , Gal Pressman , Cosmin Ratiu , Dragos Tatulea , Jiri Pirko , Jason Gunthorpe Subject: [PATCH net-next V2 00/10] net/mlx5e: Use multiple doorbells Date: Tue, 16 Sep 2025 17:11:34 +0300 Message-ID: <1758031904-634231-1-git-send-email-tariqt@nvidia.com> X-Mailer: git-send-email 2.8.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002BA4B:EE_|DM4PR12MB8571:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e344d9d-e4c5-4f03-f997-08ddf52b1485 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|7416014|82310400026|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Ac6Qes4BT0InlNZALTujHDCI4XN5QbxI1EdzhR+GhITqaYiscbZ1DEI8bKh2?= =?us-ascii?Q?19vvk+VtibTdao+SaosN7Cqr5HlHV7JyXwQh4NRzXlBFcLQ7XLVorUsjxQ9f?= =?us-ascii?Q?G8AkXQyDj82ytkRWaK0qlx6tjmKb6fL3XWUelG2r+HrRvHBXAFgNl8VJvfah?= =?us-ascii?Q?XRlYWQickmWapAmAtTJLlynKpkbAgpUf/aG5ZvWw9YHFMSZp/FI+yW6igTAe?= =?us-ascii?Q?nYcjSP91/VT4SY+kfuMnCPNZfRf6S+p0SZJPc5+efK5CKwidZWchPchLBZCV?= =?us-ascii?Q?ODOcWjBEUzrHk8rA0co1F8U4iJc1Sfm4P0B1Tls7Tl7TWgJbqoKieTepamBG?= =?us-ascii?Q?pLmCDB3uxlZv/mPqqYyVlP2aFDp7ccGY8q2ZSXytyATn3dE/d2PJoigC6Ori?= =?us-ascii?Q?KOflyROkE+3GEmiBJ73Fq1lzL15v43R5NhVy3HMGJG9IJqvdWnK8mX6wckmJ?= =?us-ascii?Q?EGp6EiwWjmAtbt3I9h2nPwTk/jVsp+G2KZ+8ASsDWnfaKE37MViotWm+MTFa?= =?us-ascii?Q?m5frSTtWrBiR8sqN9RWBQorEQ7GwJ8pJOeDlE0Zjqt4GJ3JW8KkWMH9ioxR/?= =?us-ascii?Q?tbSQnJ6zYs6Dn+xPHtGk7xHOVsoqR1jxrnlaagUdjNwVQrboZP/Osq0AukSX?= =?us-ascii?Q?gRJ8ra+HGi62hCghm0h8x9fwPpqWQ18J+CtK2C90UVD9RVVmzOywjmLZt+57?= =?us-ascii?Q?87rQWnZDIzAr9ar0WHnqsH/B3ftgMWnaObgKkfyeojb726Oq+qlV80dhekXU?= =?us-ascii?Q?IFnuhSR9/9Mp+UQ9vC9fljp/LFylUu3h/WwvYiniy4lMpi8/vu6rn9+cicch?= =?us-ascii?Q?fcyGOuFD6I0213WMpWX+/dlUH0n6/lVhZqact8S4MR0Ak84ZavfhM4PUSO1s?= =?us-ascii?Q?5aLeK65ff+lcUUWF6bw2VW//4iyz+yyCiBx2bJ2dZ3TgW+AgnRq5M1VeO4DE?= =?us-ascii?Q?nCRFRdhCh1wk9G/X2OseD2y2gceD7BP9069ebRMh29rHD3nAiRvgi7wl9o4F?= =?us-ascii?Q?23+yuPJj5xr5btZks+BLKr4ybuIv+jr1f8hZmcy9kDVsdLyEAJn0Vtp/IYCF?= =?us-ascii?Q?R2EEQlIi4iX2p0orf9Jkx20Z5PCfWQpN7+8aD1XYfr+GSWsgsDMOlWbaqr99?= =?us-ascii?Q?M/es2zqNrhhl1AXdd4L/IUEEaIVFpdRk1ZUJBlk035tZoKlCMEQ+czDYV+V6?= =?us-ascii?Q?EJ9GbOV02GHcoST9pNSEb30zJB9Cg/JOX1eWQQmAVlamwo2xvXnNzDDkqDmf?= =?us-ascii?Q?xfJTJqd1krxSlBP3HJMkL/rpVsWN+dWSYm/F6/Pcvh4wvKyGZQKs2HiRAWzV?= =?us-ascii?Q?RBu3jBah7zYSTTXHulGcQ0Ggm78KEY5wOtIi63MYYbcUqmlWZEmuedFF8+Za?= =?us-ascii?Q?WSyha4UfPBXuhOLHG4TNKeffiNi4Ob3nFZfLkjADNXLB2Jaye2L41N7OBw+k?= =?us-ascii?Q?6OCy8tmfMNTjkI2T+qitKcsjVf81SHCUeAYuHUe3b+oNIwMCDYSFWQaxIV0u?= =?us-ascii?Q?tnYjaP1V8kYAI2uxLgtc74ti2J7NLdibPz4O8cKgpNKYCRKOAfoonFXqtg?= =?us-ascii?Q?=3D=3D?= X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(376014)(7416014)(82310400026)(36860700013);DIR:OUT;SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 16 Sep 2025 14:12:33.2287 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e344d9d-e4c5-4f03-f997-08ddf52b1485 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002BA4B.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB8571 Hi, This series by Cosmin adds multiple doorbells usage in mlx5e driver. See detailed description by Cosmin below [1]. Find V1 here: https://lore.kernel.org/all/1757499891-596641-1-git-send-email-tariqt@nvidia.com/ Regards, Tariq V1->V2: - added numbers to cover letter. - fixed mlx5.rst nested list error. - removed newline from NL_SET_ERR_MSG_FMT_MOD. [1] mlx5e uses a single MMIO-mapped doorbell per netdevice for all send and receive operations. Writes to the doorbell go over the PCIe bus directly to the device, which then services the indicated queues. On certain architectures and with sufficiently high volume of doorbell ringing (many cores, many active channels, small MTU, no GSO, etc.), the MMIO-mapped doorbell address can become contended, leading to delays in servicing writes to that address and a global slowdown of all traffic for that netdevice. mlx5 NICs have supported using multiple doorbells for many years, the mlx5_ib driver for the same hardware has been using multiple doorbells traditionally. This patch series extends the mlx5 Ethernet driver to also use multiple doorbells to solve the MMIO contention issues. By allocating and using more doorbells for all channel queues (TX and RX), the MMIO contention on any particular doorbell address is reduced significantly. The first patches are cleanups: net/mlx5: Fix typo of MLX5_EQ_DOORBEL_OFFSET net/mlx5: Remove unused 'offset' field from struct mlx5_sq_bfreg' net/mlx5e: Remove unused 'xsk' param of mlx5e_build_xdpsq_param The next patch separates the global doorbell from Ethernet-specific resources: net/mlx5: Store the global doorbell in mlx5_priv Next, plumbing to allow a different doorbell to be used for channel TX and RX queues: net/mlx5e: Prepare for using multiple TX doorbells net/mlx5e: Prepare for using different CQ doorbells Then, enable using multiple doorbells for channel queues: net/mlx5e: Use multiple TX doorbells net/mlx5e: Use multiple CQ doorbells Finally, introduce a devlink parameter to control this: devlink: Add a 'num_doorbells' driverinit param net/mlx5e: Use the 'num_doorbells' devlink param Some performance results, done with the Linux pktgen script, running b2b over Connect-X 8 NICs: samples/pktgen/pktgen_sample02_multiqueue.sh -i $NIC -s 64 -d $DST_IP \ -m $MAC -t 64 Baseline (1 doorbell): 9 Mpps This series (8 doorbells): 56 Mpps Note that pktgen without 'burst' rings the doorbell after every packet, while real packet TX using NAPI usually batches multiple pending packets with the xmit_more mechanism. So this is in essence a micro-benchmark showcasing the improvement of using multiple doorbells on platforms affected by MMIO contention. Real life traffic usually sees little movement either way. Cosmin Ratiu (10): net/mlx5: Fix typo of MLX5_EQ_DOORBEL_OFFSET net/mlx5: Remove unused 'offset' field from mlx5_sq_bfreg net/mlx5e: Remove unused 'xsk' param of mlx5e_build_xdpsq_param net/mlx5: Store the global doorbell in mlx5_priv net/mlx5e: Prepare for using multiple TX doorbells net/mlx5e: Prepare for using different CQ doorbells net/mlx5e: Use multiple TX doorbells net/mlx5e: Use multiple CQ doorbells devlink: Add a 'num_doorbells' driverinit param net/mlx5e: Use the 'num_doorbells' devlink param .../networking/devlink/devlink-params.rst | 3 ++ Documentation/networking/devlink/mlx5.rst | 9 ++++ drivers/infiniband/hw/mlx5/cq.c | 4 +- drivers/net/ethernet/mellanox/mlx5/core/cq.c | 1 - .../net/ethernet/mellanox/mlx5/core/devlink.c | 26 +++++++++++ drivers/net/ethernet/mellanox/mlx5/core/en.h | 3 ++ .../ethernet/mellanox/mlx5/core/en/params.c | 6 +-- .../ethernet/mellanox/mlx5/core/en/params.h | 2 +- .../net/ethernet/mellanox/mlx5/core/en/ptp.c | 6 ++- .../net/ethernet/mellanox/mlx5/core/en/ptp.h | 1 + .../net/ethernet/mellanox/mlx5/core/en/trap.c | 1 + .../net/ethernet/mellanox/mlx5/core/en/txrx.h | 5 +-- .../mellanox/mlx5/core/en/xsk/setup.c | 2 +- .../ethernet/mellanox/mlx5/core/en_common.c | 45 ++++++++++++++++--- .../net/ethernet/mellanox/mlx5/core/en_main.c | 37 ++++++++++++--- drivers/net/ethernet/mellanox/mlx5/core/eq.c | 8 ++-- .../ethernet/mellanox/mlx5/core/fpga/conn.c | 1 - .../net/ethernet/mellanox/mlx5/core/lib/aso.c | 8 ++-- .../net/ethernet/mellanox/mlx5/core/main.c | 11 +++-- .../mellanox/mlx5/core/steering/hws/send.c | 8 ++-- .../mellanox/mlx5/core/steering/sws/dr_send.c | 1 - drivers/net/ethernet/mellanox/mlx5/core/wc.c | 16 ++++--- include/linux/mlx5/cq.h | 1 - include/linux/mlx5/driver.h | 8 ++-- include/net/devlink.h | 4 ++ net/devlink/param.c | 5 +++ 26 files changed, 163 insertions(+), 59 deletions(-) base-commit: a4ab91f470c5c84ce0c17197c1562d29aa032340 -- 2.31.1