From: Tariq Toukan <tariqt@nvidia.com>
To: Saeed Mahameed <saeedm@nvidia.com>, Leon Romanovsky <leon@kernel.org>
Cc: Eric Dumazet <edumazet@google.com>,
Jakub Kicinski <kuba@kernel.org>, Paolo Abeni <pabeni@redhat.com>,
Andrew Lunn <andrew+netdev@lunn.ch>,
"David S. Miller" <davem@davemloft.net>,
Tariq Toukan <tariqt@nvidia.com>,
"Mark Bloch" <mbloch@nvidia.com>, <netdev@vger.kernel.org>,
<linux-rdma@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Gal Pressman <gal@nvidia.com>
Subject: [PATCH mlx5-next 0/2] mlx5-next updates 2025-09-22
Date: Mon, 22 Sep 2025 09:06:29 +0300 [thread overview]
Message-ID: <1758521191-814350-1-git-send-email-tariqt@nvidia.com> (raw)
Hi,
This series contains mlx5 shared updates as preparation for upcoming
features.
Regards,
Tariq
Mark Bloch (1):
net/mlx5: IFC add balance ID and LAG per MP group bits
Tariq Toukan (1):
net/mlx5: Add IFC bit for TIR/SQ order capability
include/linux/mlx5/mlx5_ifc.h | 11 ++++++++---
1 file changed, 8 insertions(+), 3 deletions(-)
base-commit: a3d076b0567e729d5f21a95525c4d096b1f59e79
--
2.31.1
next reply other threads:[~2025-09-22 6:07 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-22 6:06 Tariq Toukan [this message]
2025-09-22 6:06 ` [PATCH mlx5-next 1/2] net/mlx5: Add IFC bit for TIR/SQ order capability Tariq Toukan
2025-09-22 6:06 ` [PATCH mlx5-next 2/2] net/mlx5: IFC add balance ID and LAG per MP group bits Tariq Toukan
2025-09-28 7:41 ` [PATCH mlx5-next 0/2] mlx5-next updates 2025-09-22 Leon Romanovsky
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