From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 105A436C9D5; Sun, 22 Mar 2026 22:56:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774220193; cv=none; b=DCFid0RMxLxDf/WN3yr1JjJB3lik+3j8fZ1r3i/Q/SFtSfF4bG07OQwt3iex0vPYoPyHinPPr++HC4CocAzL7/2892VkSkjj1mfBzKBayx62tQQeN4wi+X7Htq65cmhNZQh9s4SEe3AdimV83xZMCAhOSkUM6h7ZPnWpQaQ72t4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774220193; c=relaxed/simple; bh=oCbRxSNH1GuDwX+8hbSmIUfP9Ox64Oewx5GCbypmbrE=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=AuXCKeS8FPHPj83KL4YTuIoxBz/Cflvg3DtBnHO/MFqzEsziH0y39y6tvB3eu5DGqs6Oipjt5s9PK4dc+/RmC1lqzu5beqdRS3FlunKSNDwbJ8Dmae3OTq5puK3ZhcqOqYzfEM5NyYiHaQdiU9wPTWXP58RbgRfwC4yOXUeyGbg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=sYfyquHH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="sYfyquHH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 7458DC19424; Sun, 22 Mar 2026 22:56:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774220192; bh=oCbRxSNH1GuDwX+8hbSmIUfP9Ox64Oewx5GCbypmbrE=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=sYfyquHHkQAVCrmwdtiaYpNhgK08pwTkqNMi3BlSAhMeQRwoQ17Kds49Lg/OGqmCL SWCjyCpgWftnu/AWJvxj/64iOQS+iQz1qj7oSPQSXyYP8N1iRfaPBeKrZykMD8KBZK mkF7FsdOUiwBjsTf7fWF+ZgCMadBvYaRAvl1ev9b/BYnFRNBNcxfCIr1Rl6/jADjGx j34+fk2qe+PBJpLOpC6vqhskMkZ0O4ZGlPMBBkNGV3nuAB1A8VXFhUcbvBO/XmYIiD T2k6JGgykJ98veW45UkW9VvkpLVAcTcn3UDeVqBUaQaaZRXr5CDguRkflSGm/UcPJc 9aEQ8oHR7u8pw== Date: Sun, 22 Mar 2026 17:56:31 -0500 From: "Rob Herring (Arm)" To: Conor Dooley Cc: Linus Walleij , Conor Dooley , Krzysztof Kozlowski , Alexandre Ghiti , Palmer Dabbelt , devicetree@vger.kernel.org, Herve Codina , Thomas Gleixner , Daire McNamara , Paul Walmsley , linux-riscv@lists.infradead.org, Albert Ou , linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Bartosz Golaszewski Subject: Re: [PATCH v13 3/5] dt-bindings: soc: microchip: document PolarFire SoC's gpio interrupt mux Message-ID: <177422019104.46273.4844839015391961546.robh@kernel.org> References: <20260318-gift-nearest-fd3ef3e4819b@spud> <20260318-whisking-steadily-91b2497f6fb9@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260318-whisking-steadily-91b2497f6fb9@spud> On Wed, 18 Mar 2026 11:04:34 +0000, Conor Dooley wrote: > From: Conor Dooley > > On PolarFire SoC there are more GPIO interrupts than there are interrupt > lines available on the PLIC, and a runtime configurable mux is used to > decide which interrupts are assigned direct connections to the PLIC & > which are relegated to sharing a line. > > Reviewed-by: Herve Codina > Signed-off-by: Conor Dooley > --- > .../soc/microchip/microchip,mpfs-irqmux.yaml | 103 ++++++++++++++++++ > .../microchip,mpfs-mss-top-sysreg.yaml | 4 + > 2 files changed, 107 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml > Reviewed-by: Rob Herring (Arm)