From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D0DD9399002; Thu, 26 Mar 2026 03:19:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774495181; cv=none; b=it6ATsJYfua/hVE/4ibMHfHIAiz+6rb4D17Oaim19nv8Om1F46LWg1BSc/sEMYSJH/pxLcPT9hsOCf73BNikm1jjIKzYDgVUKQSoPaiuFTp5Jk8AhSTMCtzz7Uf4/UzA+cMwoaMy3cMvxuGPBFyCe1CcsLPq78sPtsYJ+sKBqas= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774495181; c=relaxed/simple; bh=64GvIUh5BK+CA6321kY9KFkS39Cla/4+STtvnAwRWeg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cymlS0+iX6pRjX/LWHWa+zU/0A4R/FKnOuY0Rtw32gMdMeat6dLODBMswyykmDmxE+gI2kDsKjmXCBa7Uz57tljLZ2BZJZrmP3PwqLwdiMZQB3+9JysNw7qGbdJAeiYZGPbrVKB8odirrMZaQU4W8KcBNQzSZL1ydtnah6Q6WAY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DoNJjbvs; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DoNJjbvs" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 93B85C2BC9E; Thu, 26 Mar 2026 03:19:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774495180; bh=64GvIUh5BK+CA6321kY9KFkS39Cla/4+STtvnAwRWeg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=DoNJjbvsdO9M8I355YakZTdyuT3xoRXpGtMM2wojdApb9Q7ajDoGdWHuW7T+qyJs8 JLJtoasNll/fzCTKgF2pot1ARQr8/WJz18ymv6QdXj8Tag8zYprMsTUMGMVBz07VAn 5/ol1dU6SqblhURvBbAUXWOT7ww/gO3Zmxb6zeoa1vKQWvC6Bi4QosLSw70nx8ljqL mxsSn9BJvJy2ba4neAZFnE1z8Z2JJhzsTZs5kI0u1/lgpSiGsj2hWBD4svpQ3mlUIl XLzSUDEneP1HMa3cDTXdRO7iUfFokDI5VOrhaCtSvbUNOFApAwpcyH/ryPfTXW5PdJ 42LGsCrP7+iHQ== From: Bjorn Andersson To: Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , Peter Griffin , =?UTF-8?q?Andr=C3=A9=20Draszik?= , Tudor Ambarus , Alim Akhtar , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Dinh Nguyen , Konrad Dybcio , Thierry Reding , Marc Zyngier , Geert Uytterhoeven Cc: linux-arm-kernel@lists.infradead.org, linux-amlogic@lists.infradead.org, linux-samsung-soc@vger.kernel.org, imx@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: (subset) [PATCH 0/7] arm64: dts: Drop CPU masks from GICv3 PPI interrupts Date: Wed, 25 Mar 2026 22:19:21 -0500 Message-ID: <177449516624.60308.16445349174496027428.b4-ty@kernel.org> X-Mailer: git-send-email 2.53.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit On Wed, 04 Mar 2026 18:10:57 +0100, Geert Uytterhoeven wrote: > Hi all, > > Unlike older GIC variants, the GICv3 DT bindings do not support > specifying a CPU mask in PPI interrupt specifiers. Hence this patch > series drop all such masks where they are still present. > > This has been compile-tested only. But note that all such masks were > removed before from Renesas SoCs in commit 8b6a006c914aac17 ("arm64: > dts: renesas: Drop specifying the GIC_CPU_MASK_SIMPLE() for GICv3 > systems")). > > [...] Applied, thanks! [7/7] arm64: dts: qcom: Drop CPU masks from GICv3 PPI interrupts commit: 99bb0693df91db9338fa69d496de4601c9582058 Best regards, -- Bjorn Andersson