[PATCH v2 4/7] arm64: dts: qcom: milos: Split up uart11 pinctrl

Luca Weiss
2026-04-03T13:55:22Z

In order to set the pinctrl for the individual CTS, RTS, TX and RX pins,
split up the pinctrl configuration into 4 nodes so that boards can set
some properties separately.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
---
arch/arm64/boot/dts/qcom/milos.dtsi | 28 ++++++++++++++++++----------
1 file changed, 18 insertions(+), 10 deletions(-)

diff --git a/arch/arm64/boot/dts/qcom/milos.dtsi b/arch/arm64/boot/dts/qcom/milos.dtsi
index 4a64a98a434b..71292dfd6e08 100644
--- a/arch/arm64/boot/dts/qcom/milos.dtsi
+++ b/arch/arm64/boot/dts/qcom/milos.dtsi
@@ -2099,19 +2099,27 @@ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
};

qup_uart11_cts_rts: qup-uart11-cts-rts-state {
- /* CTS, RTS */
- pins = "gpio48", "gpio49";
- function = "qup1_se4";
- drive-strength = <2>;
- bias-pull-down;
+ qup_uart11_cts: cts-pins {
+ pins = "gpio48";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_rts: rts-pins {
+ pins = "gpio49";
+ function = "qup1_se4";
+ };
};

qup_uart11_default: qup-uart11-default-state {
- /* TX, RX */
- pins = "gpio50", "gpio51";
- function = "qup1_se4";
- drive-strength = <2>;
- bias-pull-up;
+ qup_uart11_tx: tx-pins {
+ pins = "gpio50";
+ function = "qup1_se4";
+ };
+
+ qup_uart11_rx: rx-pins {
+ pins = "gpio51";
+ function = "qup1_se4";
+ };
};

sdc2_default: sdc2-default-state {

--
2.53.0