Re: [PATCH v8 00/22] Add Counter delegation ISA extension support

[patchwork-bot+linux-riscv@kernel.org]

Hello:

This series was applied to riscv/linux.git (for-next)
by Paul Walmsley <pjw@kernel.org>:

On Wed, 01 Jul 2026 01:46:48 -0700 you wrote:
> This series adds the counter delegation extension support. It is based on
> very early PoC work done by Kevin Xue and mostly rewritten after that.
> The counter delegation ISA extension(Smcdeleg/Ssccfg) actually depends
> on multiple ISA extensions.
> 
> 1. S[m|s]csrind : The indirect CSR extension[1] which defines additional
>    5 ([M|S|VS]IREG2-[M|S|VS]IREG6) register to address size limitation of
>    RISC-V CSR address space.
> 2. Smstateen: The stateen bit[60] controls the access to the registers
>    indirectly via the above indirect registers.
> 3. Smcdeleg/Ssccfg: The counter delegation extensions[2]
> 
> [...]

Here is the summary with links:
  - [v8,01/22] RISC-V: perf: fix resource cleanup on driver probe failure
    https://git.kernel.org/riscv/c/bf08074d8a20
  - [v8,02/22] RISC-V: Add Sxcsrind ISA extension CSR definitions
    https://git.kernel.org/riscv/c/7c31031b2974
  - [v8,03/22] RISC-V: Add Sxcsrind ISA extension definition and parsing
    https://git.kernel.org/riscv/c/7fe9435ef9e7
  - [v8,04/22] dt-bindings: riscv: add Sxcsrind ISA extension description
    https://git.kernel.org/riscv/c/010e2b79bd08
  - [v8,05/22] RISC-V: Define indirect CSR access helpers
    https://git.kernel.org/riscv/c/6f1ece4a6691
  - [v8,06/22] RISC-V: Add Smcntrpmf extension parsing
    https://git.kernel.org/riscv/c/935bfae38e57
  - [v8,07/22] dt-bindings: riscv: add Smcntrpmf ISA extension description
    https://git.kernel.org/riscv/c/837eaefa4d63
  - [v8,08/22] RISC-V: Add Sscfg extension CSR definition
    https://git.kernel.org/riscv/c/db40f62b80ec
  - [v8,09/22] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing
    https://git.kernel.org/riscv/c/2ea70441fe0f
  - [v8,10/22] dt-bindings: riscv: add Counter delegation ISA extensions description
    https://git.kernel.org/riscv/c/b8d69e7159cc
  - [v8,11/22] RISC-V: perf: Restructure the SBI PMU code
    (no matching commit)
  - [v8,12/22] RISC-V: perf: Modify the counter discovery mechanism
    (no matching commit)
  - [v8,13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding
    (no matching commit)
  - [v8,14/22] RISC-V: perf: Implement supervisor counter delegation support
    (no matching commit)
  - [v8,15/22] RISC-V: perf: Skip PMU SBI extension when not implemented
    (no matching commit)
  - [v8,16/22] RISC-V: perf: Use config2/vendor table for event to counter mapping
    (no matching commit)
  - [v8,17/22] RISC-V: perf: Add legacy event encodings via sysfs
    (no matching commit)
  - [v8,18/22] RISC-V: perf: Add Qemu virt machine events
    (no matching commit)
  - [v8,19/22] tools/perf: Support event code for arch standard events
    (no matching commit)
  - [v8,20/22] tools/perf: Add RISC-V CounterIDMask event field
    (no matching commit)
  - [v8,21/22] TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing
    (no matching commit)
  - [v8,22/22] TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path
    (no matching commit)

You are awesome, thank you!
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