From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B553BCCA47C for ; Thu, 23 Jun 2022 16:32:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232209AbiFWQcA convert rfc822-to-8bit (ORCPT ); Thu, 23 Jun 2022 12:32:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33998 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231837AbiFWQb4 (ORCPT ); Thu, 23 Jun 2022 12:31:56 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BF3746B28 for ; Thu, 23 Jun 2022 09:31:53 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=diego.localnet) by gloria.sntech.de with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o4PkE-0002xb-Gk; Thu, 23 Jun 2022 18:31:50 +0200 From: Heiko =?ISO-8859-1?Q?St=FCbner?= To: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Palmer Dabbelt , Paul Walmsley , Albert Ou , Philipp Tomsich , Aaron Durbin , Randy Dunlap , Atish Patra , Christoph Muellner Cc: Christoph =?ISO-8859-1?Q?M=FCllner?= Subject: Re: [RFC PATCH v2] riscv: Add Zawrs support for spinlocks Date: Thu, 23 Jun 2022 18:31:49 +0200 Message-ID: <1903087.PYKUYFuaPT@diego> In-Reply-To: <20220623152948.1607295-1-christoph.muellner@vrull.eu> References: <20220623152948.1607295-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 Content-Transfer-Encoding: 8BIT Content-Type: text/plain; charset="iso-8859-1" Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Christoph, Am Donnerstag, 23. Juni 2022, 17:29:48 CEST schrieb Christoph Muellner: > From: Christoph Müllner > > The current RISC-V code uses the generic ticket lock implementation, > that calls the macros smp_cond_load_relaxed() and smp_cond_load_acquire(). > Currently, RISC-V uses the generic implementation of these macros. > This patch introduces a RISC-V specific implementation, of these > macros, that peels off the first loop iteration and modifies the waiting > loop such, that it is possible to use the WRS.STO instruction of the Zawrs > ISA extension to stall the CPU. > > The resulting implementation of smp_cond_load_*() will only work for > 32-bit or 64-bit types for RV64 and 32-bit types for RV32. > This is caused by the restrictions of the LR instruction (RISC-V only > has LR.W and LR.D). Compiler assertions guard this new restriction. > > This patch uses the existing RISC-V ISA extension framework > to detect the presents of Zawrs at run-time. > If available a NOP instruction will be replaced by WRS.NTO or WRS.STO. > > The whole mechanism is gated by Kconfig setting, which defaults to Y. > > The Zawrs specification can be found here: > https://github.com/riscv/riscv-zawrs/blob/main/zawrs.adoc > > Note, that the Zawrs extension is not frozen or ratified yet. > Therefore this patch is an RFC and not intended to get merged. > > Changes since v1: > * Adding "depends on !XIP_KERNEL" to RISCV_ISA_ZAWRS > * Fixing type checking code in __smp_load_reserved* > * Adjustments according to the specification change > > Signed-off-by: Christoph Müllner With the matching Qemu-Patch on - rv64 + Debian rootfs - rv32 + 32bit-Buildroot rootfs Tested-by: Heiko Stuebner apart from the one nit below Reviewed-by: Heiko Stuebner > --- > arch/riscv/Kconfig | 11 ++++ > arch/riscv/include/asm/barrier.h | 92 ++++++++++++++++++++++++++++ > arch/riscv/include/asm/errata_list.h | 19 +++++- > arch/riscv/include/asm/hwcap.h | 3 +- > arch/riscv/kernel/cpu.c | 1 + > arch/riscv/kernel/cpufeature.c | 13 ++++ > 6 files changed, 136 insertions(+), 3 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 32ffef9f6e5b..9d40569237c9 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -358,6 +358,17 @@ config RISCV_ISA_C > > If you don't know what to do here, say Y. > > +config RISCV_ISA_ZAWRS > + bool "Zawrs extension support" > + depends on !XIP_KERNEL > + select RISCV_ALTERNATIVE > + default y > + help > + Adds support to dynamically detect the presence of the Zawrs extension > + (wait for reservation set) and enable its usage. > + > + If you don't know what to do here, say Y. > + > config RISCV_ISA_SVPBMT > bool "SVPBMT extension support" > depends on 64BIT && MMU > diff --git a/arch/riscv/include/asm/barrier.h b/arch/riscv/include/asm/barrier.h > index d0e24aaa2aa0..1f9628aaa7cb 100644 > --- a/arch/riscv/include/asm/barrier.h > +++ b/arch/riscv/include/asm/barrier.h > @@ -12,6 +12,8 @@ > > #ifndef __ASSEMBLY__ > > +#include > + > #define nop() __asm__ __volatile__ ("nop") > > #define RISCV_FENCE(p, s) \ > @@ -42,6 +44,64 @@ do { \ > ___p1; \ > }) > > +#if __riscv_xlen == 64 > + nit: I guess we could do without the extra blanks? asm.h does so, and also the #else block below also doesn't use them ;-) . But I guess that is more a style debate > +#define __riscv_lrsc_word(t) \ > + (sizeof(t) == sizeof(int) || \ > + sizeof(t) == sizeof(long)) > + > +#elif __riscv_xlen == 32 > + > +#define __riscv_lrsc_word(t) \ > + (sizeof(t) == sizeof(int)) > + > +#else > +#error "Unexpected __riscv_xlen" > +#endif /* __riscv_xlen */ [...] Thanks Heiko