Re: [PATCH 04/20] arm64: dts: qcom: kaanapali: Add support for PCIe0 on Kaanapali

Konrad Dybcio
2025-09-25T10:56:14Z

On 9/25/25 2:17 AM, Jingyi Wang wrote:
> From: Qiang Yu <qiang.yu@oss.qualcomm.com>
>
> Describe PCIe0 controller and PHY. Also add required system resources like
> regulators, clocks, interrupts and registers configuration for PCIe0.
>
> Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
> Signed-off-by: Jingyi Wang <jingyi.wang@oss.qualcomm.com>
> ---

[...]

> +
> + pcieport0: pcie@0 {

"pcie0_port0:"

> + device_type = "pci";
> + reg = <0x0 0x0 0x0 0x0 0x0>;
> + bus-range = <0x01 0xff>;
> +
> + #address-cells = <3>;
> + #size-cells = <2>;
> + ranges;
> + phys = <&pcie0_phy>;

how about:

device_type = "pci";
reg = <0x0 0x0 0x0 0x0 0x0>;
bus-range = <0x01 0xff>;

phys = <&pcie0_phy>;

#address-cells = <3>;
#size-cells = <2>;
ranges;

with that:

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>

Konrad