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Mon, 05 May 2025 03:36:18 -0700 (PDT) Message-ID: <1a403393-e317-4a1b-a151-fa668c6278f9@gmail.com> Date: Mon, 5 May 2025 06:36:16 -0400 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/3] arm64: dts: rockchip: Add Luckfox Omni3576 Board support To: Andrew Lunn Cc: Jonas Karlman , heiko@sntech.de, robh@kernel.org, conor+dt@kernel.org, detlev.casanova@collabora.com, linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, krzk+dt@kernel.org, linux-arm-kernel@lists.infradead.org References: <20250502205533.51744-1-inindev@gmail.com> <20250504102447.153551-1-inindev@gmail.com> <20250504102447.153551-4-inindev@gmail.com> <87892840-bdbf-43d4-bd93-cb98f5e1c672@lunn.ch> <46cbdabd-b0ed-4c9b-9f01-4d2d8eceac24@gmail.com> <13407dae-4c73-48a9-846e-92f08449bc4d@lunn.ch> Content-Language: en-US From: John Clark In-Reply-To: <13407dae-4c73-48a9-846e-92f08449bc4d@lunn.ch> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit On 5/4/25 8:45 PM, Andrew Lunn wrote: >>> What PHY is it? Are you using the correct PHY driver for it, or >>> genphy? >>> >> MAE0621A-Q3C >> http://www.maxio-tech.com/product/12928/12929/12930/12931.html > > Mainline does not have a PHY driver for this. So nothing is > controlling the delays in the PHY. So what you have above works by > luck, and is likely to break once there is a PHY driver. So i suggest > you drop the Ethernet nodes for the moment. > > There does appear to be a PHY driver here: > > https://github.com/CoreELEC/linux-amlogic/blob/5.15.153_202501/drivers/net/phy/maxio.c > > but it has a number of things wrong with it. You might want to search > around and see if there are any cleaner versions around, or if anybody > is working on upstreaming a driver for this PHY. > > Andrew > Hi Andrew, Thank you for your valuable feedback and for pointing me toward investigating the PHY configuration further. After digging deeper into the MAE0621A-Q3C PHY (PHY ID 0x7b744412), I now understand why it performs reliably: the generic PHY driver relies on the GMAC to set RGMII delays (tx_delay=0x20, rx_delay=0x10), enabling a stable 1Gbps link for gmac0 in rgmii-rxid mode, while rgmii-id failed in my tests due to the driver’s lack of internal delay configuration. Given the critical role of networking for development, I’d like to retain the GMAC nodes in v3 using this setup, but I’d greatly appreciate your approval on whether the generic PHY driver is suitable in rgmii-rxid mode for now. I’m eager to explore a Maxio-specific driver for mainline compatibility and would be grateful for any guidance on existing upstreaming efforts for this PHY. Best regards, John