[PATCH v4 0/7] riscv: Add support for xmipsexectl

[PATCH v4 0/7] riscv: Add support for xmipsexectl

[Aleksa Paunovic via B4 Relay]

This patch series adds support for the xmipsexectl vendor extension.
A new hardware probe key has also been added to allow userspace to probe for MIPS vendor extensions.

Additionally, since the standard Zihintpause PAUSE instruction encoding is not supported on some MIPS CPUs,
an errata was implemented for replacing this instruction with the xmipsexectl MIPS.PAUSE alternative encoding.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
This is a continuation of a previous series, which did not implement the full
xmipsexectl vendor extension. The title was updated accordingly.

Changes in v4:
- Add support for the xmipsexectl vendor extension
- Remove the ifdef/else from errata_list.h
- Replace the ifdef/else with a hwprobe call in the userspace code.

Link to v3:
https://lore.kernel.org/linux-riscv/20250129131703.733098-1-arikalo@gmail.com/

---
Aleksa Paunovic (6):
      dt-bindings: riscv: Add xmipsexectl ISA extension description
      riscv: Add xmipsexectl as a vendor extension
      riscv: Add xmipsexectl PAUSE instruction
      riscv: hwprobe: Add MIPS vendor extension probing
      riscv: hwprobe: Document MIPS xmipsexectl vendor extension
      riscv: Add tools support for xmipsexectl

Djordje Todorovic (1):
      riscv: errata: Fix the PAUSE Opcode for MIPS P8700

 Documentation/arch/riscv/hwprobe.rst               |  9 +++
 .../devicetree/bindings/riscv/extensions.yaml      |  6 ++
 arch/riscv/Kconfig.errata                          | 23 ++++++++
 arch/riscv/Kconfig.vendor                          | 13 +++++
 arch/riscv/errata/Makefile                         |  1 +
 arch/riscv/errata/mips/Makefile                    |  5 ++
 arch/riscv/errata/mips/errata.c                    | 67 ++++++++++++++++++++++
 arch/riscv/include/asm/alternative.h               |  3 +
 arch/riscv/include/asm/cmpxchg.h                   |  3 +-
 arch/riscv/include/asm/errata_list.h               | 17 +++++-
 arch/riscv/include/asm/hwprobe.h                   |  3 +-
 arch/riscv/include/asm/vdso/processor.h            |  4 +-
 arch/riscv/include/asm/vendor_extensions/mips.h    | 23 ++++++++
 .../include/asm/vendor_extensions/mips_hwprobe.h   | 23 ++++++++
 arch/riscv/include/asm/vendorid_list.h             |  1 +
 arch/riscv/include/uapi/asm/hwprobe.h              |  1 +
 arch/riscv/include/uapi/asm/vendor/mips.h          |  3 +
 arch/riscv/kernel/alternative.c                    |  5 ++
 arch/riscv/kernel/entry.S                          |  2 +
 arch/riscv/kernel/sys_hwprobe.c                    |  4 ++
 arch/riscv/kernel/vendor_extensions.c              | 10 ++++
 arch/riscv/kernel/vendor_extensions/Makefile       |  2 +
 arch/riscv/kernel/vendor_extensions/mips.c         | 22 +++++++
 arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 22 +++++++
 arch/riscv/mm/init.c                               |  1 +
 tools/arch/riscv/include/asm/vdso/processor.h      | 27 +++++----
 26 files changed, 286 insertions(+), 14 deletions(-)
---
base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
change-id: 20250424-p8700-pause-dcb649968e24

Best regards,
-- 
Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

[PATCH v4 1/7] dt-bindings: riscv: Add xmipsexectl ISA extension description

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

The xmipsexectl extension is described in the MIPS RV64 P8700/P8700-F
Multiprocessing System Programmer’s Guide linked at [1].

Link: https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ede6a58ccf5347d92785dc085a011052c1aade14..de41a6f074d3af2ceaf5293dfe75d16f43d416d6 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -662,6 +662,12 @@ properties:
             Registers in the AX45MP datasheet.
             https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
 
+        # MIPS
+        - const: xmipsexectl
+          description:
+            The MIPS extension for execution control as documented in
+            https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
+
         # SiFive
         - const: xsfvqmaccdod
           description:

-- 
2.34.1

[PATCH v4 2/7] riscv: Add xmipsexectl as a vendor extension

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add support for MIPS vendor extensions. Add support for the xmipsexectl
vendor extension.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/Kconfig.vendor                       | 13 +++++++++++++
 arch/riscv/include/asm/vendor_extensions/mips.h | 16 ++++++++++++++++
 arch/riscv/kernel/vendor_extensions.c           | 10 ++++++++++
 arch/riscv/kernel/vendor_extensions/Makefile    |  1 +
 arch/riscv/kernel/vendor_extensions/mips.c      | 22 ++++++++++++++++++++++
 5 files changed, 62 insertions(+)

diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor
index e14f26368963c178e3271e0f716b27fff7671e78..3c1f92e406c3f21481b56e61229716fd02ab81b2 100644
--- a/arch/riscv/Kconfig.vendor
+++ b/arch/riscv/Kconfig.vendor
@@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES
 	  If you don't know what to do here, say Y.
 endmenu
 
+menu "MIPS"
+config RISCV_ISA_VENDOR_EXT_MIPS
+	bool "MIPS vendor extension support"
+	select RISCV_ISA_VENDOR_EXT
+	default y
+	help
+	  Say N here to disable detection of and support for all MIPS vendor
+	  extensions. Without this option enabled, MIPS vendor extensions will
+	  not be detected at boot and their presence not reported to userspace.
+
+	  If you don't know what to do here, say Y.
+endmenu
+
 menu "SiFive"
 config RISCV_ISA_VENDOR_EXT_SIFIVE
 	bool "SiFive vendor extension support"
diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h
new file mode 100644
index 0000000000000000000000000000000000000000..757c941cfd86e9fced6169b1a82200e6bb5c6132
--- /dev/null
+++ b/arch/riscv/include/asm/vendor_extensions/mips.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 MIPS.
+ */
+
+#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
+#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
+
+#include <asm/vendor_extensions.h>
+#include <linux/types.h>
+
+#define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL	0
+
+extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
+
+#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
index 92d8ff81f42c9ceba63bef0170ab134564a24a4e..bb4a7592368560ebacbcd8a5ce335eea6312ea5c 100644
--- a/arch/riscv/kernel/vendor_extensions.c
+++ b/arch/riscv/kernel/vendor_extensions.c
@@ -6,6 +6,7 @@
 #include <asm/vendorid_list.h>
 #include <asm/vendor_extensions.h>
 #include <asm/vendor_extensions/andes.h>
+#include <asm/vendor_extensions/mips.h>
 #include <asm/vendor_extensions/sifive.h>
 #include <asm/vendor_extensions/thead.h>
 
@@ -16,6 +17,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = {
 #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
 	&riscv_isa_vendor_ext_list_andes,
 #endif
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
+	&riscv_isa_vendor_ext_list_mips,
+#endif
 #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
 	&riscv_isa_vendor_ext_list_sifive,
 #endif
@@ -49,6 +53,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
 		cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;
 		break;
 	#endif
+	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
+	case MIPS_VENDOR_ID:
+		bmap = &riscv_isa_vendor_ext_list_mips.all_harts_isa_bitmap;
+		cpu_bmap = riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap;
+		break;
+	#endif
 	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
 	case SIFIVE_VENDOR_ID:
 		bmap = &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap;
diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
index a4eca96d1c8a2fd165220f6439a3884cf90a9593..ccad4ebafb43412e72e654da3bdb9face53b80c6 100644
--- a/arch/riscv/kernel/vendor_extensions/Makefile
+++ b/arch/riscv/kernel/vendor_extensions/Makefile
@@ -1,6 +1,7 @@
 # SPDX-License-Identifier: GPL-2.0-only
 
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o
+obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips.o
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive.o
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive_hwprobe.o
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o
diff --git a/arch/riscv/kernel/vendor_extensions/mips.c b/arch/riscv/kernel/vendor_extensions/mips.c
new file mode 100644
index 0000000000000000000000000000000000000000..f691129f96c21f2ef089124f4b64a6f0a8e6d4aa
--- /dev/null
+++ b/arch/riscv/kernel/vendor_extensions/mips.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 MIPS.
+ */
+
+#include <asm/cpufeature.h>
+#include <asm/vendor_extensions.h>
+#include <asm/vendor_extensions/mips.h>
+
+#include <linux/array_size.h>
+#include <linux/cpumask.h>
+#include <linux/types.h>
+
+/* All MIPS vendor extensions supported in Linux */
+static const struct riscv_isa_ext_data riscv_isa_vendor_ext_mips[] = {
+	__RISCV_ISA_EXT_DATA(xmipsexectl, RISCV_ISA_VENDOR_EXT_XMIPSEXECTL),
+};
+
+struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips = {
+	.ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_mips),
+	.ext_data = riscv_isa_vendor_ext_mips,
+};

-- 
2.34.1

[PATCH v4 3/7] riscv: Add xmipsexectl PAUSE instruction

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add MIPS.PAUSE instruction opcode. This instruction is a part of the
xmipsexectl vendor extension.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/include/asm/vendor_extensions/mips.h | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h
index 757c941cfd86e9fced6169b1a82200e6bb5c6132..f8eca0bcf53e2de1bbdc66821fe95987105ed85a 100644
--- a/arch/riscv/include/asm/vendor_extensions/mips.h
+++ b/arch/riscv/include/asm/vendor_extensions/mips.h
@@ -13,4 +13,11 @@
 
 extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
 
+/* MIPS.PAUSE is an alternative opcode which is implemented to have the */
+/* same behavior as PAUSE on some MIPS RISCV cores. */
+/* It is a ‘hint’ encoding of the SLLI instruction, */
+/* with rd = 0, rs1 = 0 and imm = 5. */
+
+#define MIPS_PAUSE	".4byte 0x00501013\n\t"
+
 #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H

-- 
2.34.1

[PATCH v4 4/7] riscv: hwprobe: Add MIPS vendor extension probing

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" which allows
userspace to probe for the new xmipsexectl vendor extension.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/include/asm/hwprobe.h                   |  3 ++-
 .../include/asm/vendor_extensions/mips_hwprobe.h   | 23 ++++++++++++++++++++++
 arch/riscv/include/uapi/asm/hwprobe.h              |  1 +
 arch/riscv/include/uapi/asm/vendor/mips.h          |  3 +++
 arch/riscv/kernel/sys_hwprobe.c                    |  4 ++++
 arch/riscv/kernel/vendor_extensions/Makefile       |  1 +
 arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 22 +++++++++++++++++++++
 7 files changed, 56 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
index 7fe0a379474ae2c64d300d6fee4a012173f6a6d7..948d2b34e94e84e4c2c351ffe91f4b3afcefc3f7 100644
--- a/arch/riscv/include/asm/hwprobe.h
+++ b/arch/riscv/include/asm/hwprobe.h
@@ -8,7 +8,7 @@
 
 #include <uapi/asm/hwprobe.h>
 
-#define RISCV_HWPROBE_MAX_KEY 13
+#define RISCV_HWPROBE_MAX_KEY 14
 
 static inline bool riscv_hwprobe_key_is_valid(__s64 key)
 {
@@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key)
 	case RISCV_HWPROBE_KEY_IMA_EXT_0:
 	case RISCV_HWPROBE_KEY_CPUPERF_0:
 	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
+	case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
 	case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
 		return true;
 	}
diff --git a/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
new file mode 100644
index 0000000000000000000000000000000000000000..0af8c07c22f293b5f772709f774de78dd60c7f39
--- /dev/null
+++ b/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2025 MIPS.
+ */
+
+#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
+#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
+
+#include <linux/cpumask.h>
+#include <uapi/asm/hwprobe.h>
+
+
+#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
+void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
+#else
+static inline void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
+						 const struct cpumask *cpus)
+{
+	pair->value = 0;
+}
+#endif
+
+#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index aaf6ad97049931381f9542bb9316c873ec6ab9f6..5d30a4fae37a82ef4d968d20b187420772ad8946 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -106,6 +106,7 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0	11
 #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE	12
 #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13
+#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
 /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
 
 /* Flags */
diff --git a/arch/riscv/include/uapi/asm/vendor/mips.h b/arch/riscv/include/uapi/asm/vendor/mips.h
new file mode 100644
index 0000000000000000000000000000000000000000..11d41651178233a5f06ab9541ea0506d9883aa19
--- /dev/null
+++ b/arch/riscv/include/uapi/asm/vendor/mips.h
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
+
+#define RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL	(1 << 0)
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 0b170e18a2beba576f4f8787d6ef6aa67c5c3d0e..6c73e167ef4ccc7f99dd2793acde2595fffdcbad 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -15,6 +15,7 @@
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
 #include <asm/vector.h>
+#include <asm/vendor_extensions/mips_hwprobe.h>
 #include <asm/vendor_extensions/sifive_hwprobe.h>
 #include <asm/vendor_extensions/thead_hwprobe.h>
 #include <vdso/vsyscall.h>
@@ -309,6 +310,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
 		hwprobe_isa_vendor_ext_thead_0(pair, cpus);
 		break;
+	case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
+		hwprobe_isa_vendor_ext_mips_0(pair, cpus);
+		break;
 
 	/*
 	 * For forward compatibility, unknown keys don't fail the whole
diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
index ccad4ebafb43412e72e654da3bdb9face53b80c6..bf116c82b6bdb3aee23e27fc0b2a69be7c7a5ccb 100644
--- a/arch/riscv/kernel/vendor_extensions/Makefile
+++ b/arch/riscv/kernel/vendor_extensions/Makefile
@@ -2,6 +2,7 @@
 
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips.o
+obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips_hwprobe.o
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive.o
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive_hwprobe.o
 obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o
diff --git a/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c b/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
new file mode 100644
index 0000000000000000000000000000000000000000..43944f2b484af257fa358cda53c12b4d6f54b78b
--- /dev/null
+++ b/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 MIPS.
+ */
+
+#include <asm/vendor_extensions/mips.h>
+#include <asm/vendor_extensions/mips_hwprobe.h>
+#include <asm/vendor_extensions/vendor_hwprobe.h>
+
+#include <linux/cpumask.h>
+#include <linux/types.h>
+
+#include <uapi/asm/hwprobe.h>
+#include <uapi/asm/vendor/mips.h>
+
+void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
+				   const struct cpumask *cpus)
+{
+	VENDOR_EXTENSION_SUPPORTED(
+		pair, cpus, riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap,
+		{ VENDOR_EXT_KEY(XMIPSEXECTL); });
+}

-- 
2.34.1

[PATCH v4 5/7] riscv: hwprobe: Document MIPS xmipsexectl vendor extension

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Document support for MIPS vendor extensions using the key
"RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" and xmipsexectl vendor extension
using the key "RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL".

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 Documentation/arch/riscv/hwprobe.rst | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
index 2aa9be272d5de1c15559a978a956bc36c34de81c..2f449c9b15bdd6b9813c9a968deca1a4c4ff9b14 100644
--- a/Documentation/arch/riscv/hwprobe.rst
+++ b/Documentation/arch/riscv/hwprobe.rst
@@ -327,6 +327,15 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are
     not supported at all and will generate a misaligned address fault.
 
+* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the
+  mips vendor extensions that are compatible with the
+  :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
+
+  * MIPS
+
+    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor
+        extension is supported in the MIPS ISA extensions spec.
+
 * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the
   thead vendor extensions that are compatible with the
   :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.

-- 
2.34.1

[PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Aleksa Paunovic via B4 Relay]

From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>

Use the hwprobe syscall to decide which PAUSE instruction to execute in
userspace code.

Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
 1 file changed, 17 insertions(+), 10 deletions(-)

diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
--- a/tools/arch/riscv/include/asm/vdso/processor.h
+++ b/tools/arch/riscv/include/asm/vdso/processor.h
@@ -4,26 +4,33 @@
 
 #ifndef __ASSEMBLY__
 
+#include <asm/hwprobe.h>
+#include <sys/hwprobe.h>
+#include <asm/vendor/mips.h>
 #include <asm-generic/barrier.h>
 
 static inline void cpu_relax(void)
 {
+	struct riscv_hwprobe pair;
+	bool has_mipspause;
 #ifdef __riscv_muldiv
 	int dummy;
 	/* In lieu of a halt instruction, induce a long-latency stall. */
 	__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
 #endif
 
-#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
-	/*
-	 * Reduce instruction retirement.
-	 * This assumes the PC changes.
-	 */
-	__asm__ __volatile__ ("pause");
-#else
-	/* Encoding of the pause instruction */
-	__asm__ __volatile__ (".4byte 0x100000F");
-#endif
+	pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
+	__riscv_hwprobe(&pair, 1, 0, NULL, 0);
+	has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
+
+	if (has_mipspause) {
+		/* Encoding of the mips pause instruction */
+		__asm__ __volatile__(".4byte 0x00501013");
+	} else {
+		/* Encoding of the pause instruction */
+		__asm__ __volatile__(".4byte 0x100000F");
+	}
+
 	barrier();
 }
 

-- 
2.34.1

[PATCH v4 7/7] riscv: errata: Fix the PAUSE Opcode for MIPS P8700

[Aleksa Paunovic via B4 Relay]

From: Djordje Todorovic <djordje.todorovic@htecgroup.com>

Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.
Handle errata for the MIPS PAUSE instruction.

Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
Signed-off-by: Raj Vishwanathan4 <rvishwanathan@mips.com>
Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
---
 arch/riscv/Kconfig.errata               | 23 +++++++++++
 arch/riscv/errata/Makefile              |  1 +
 arch/riscv/errata/mips/Makefile         |  5 +++
 arch/riscv/errata/mips/errata.c         | 67 +++++++++++++++++++++++++++++++++
 arch/riscv/include/asm/alternative.h    |  3 ++
 arch/riscv/include/asm/cmpxchg.h        |  3 +-
 arch/riscv/include/asm/errata_list.h    | 17 ++++++++-
 arch/riscv/include/asm/vdso/processor.h |  4 +-
 arch/riscv/include/asm/vendorid_list.h  |  1 +
 arch/riscv/kernel/alternative.c         |  5 +++
 arch/riscv/kernel/entry.S               |  2 +
 arch/riscv/mm/init.c                    |  1 +
 12 files changed, 129 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
index e318119d570de0acc0850a2e1a2505ecb71bea08..aca9b0cfcfecf91d4d1910f294ee109ed15f2d6c 100644
--- a/arch/riscv/Kconfig.errata
+++ b/arch/riscv/Kconfig.errata
@@ -21,6 +21,29 @@ config ERRATA_ANDES_CMO
 
 	  If you don't know what to do here, say "Y".
 
+config ERRATA_MIPS
+	bool "MIPS errata"
+	depends on RISCV_ALTERNATIVE
+	help
+	  All MIPS errata Kconfig depend on this Kconfig. Disabling
+	  this Kconfig will disable all MIPS errata. Please say "Y"
+	  here if your platform uses MIPS CPU cores.
+
+	  Otherwise, please say "N" here to avoid unnecessary overhead.
+
+config ERRATA_MIPS_P8700_PAUSE_OPCODE
+	bool "Fix the PAUSE Opcode for MIPS P8700"
+	depends on ERRATA_MIPS && 64BIT
+	default n
+	help
+	   The RISCV MIPS P8700 uses a different opcode for PAUSE.
+	   It is a 'hint' encoding of the SLLI instruction,
+	   with rd=0, rs1=0 and imm=5. It will behave as a NOP
+	   instruction if no additional behavior beyond that of
+	   SLLI is implemented.
+
+	   If you are not using the P8700 processor, say n.
+
 config ERRATA_SIFIVE
 	bool "SiFive errata"
 	depends on RISCV_ALTERNATIVE
diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
index bc6c77ba837d2da4c98dabab18083d27f46629c7..02a7a3335b1d557933e04cd6d0cf7bf4260b8c40 100644
--- a/arch/riscv/errata/Makefile
+++ b/arch/riscv/errata/Makefile
@@ -13,5 +13,6 @@ endif
 endif
 
 obj-$(CONFIG_ERRATA_ANDES) += andes/
+obj-$(CONFIG_ERRATA_MIPS) += mips/
 obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
 obj-$(CONFIG_ERRATA_THEAD) += thead/
diff --git a/arch/riscv/errata/mips/Makefile b/arch/riscv/errata/mips/Makefile
new file mode 100644
index 0000000000000000000000000000000000000000..6278c389b801ee6e54e808c80e6e236c026329c7
--- /dev/null
+++ b/arch/riscv/errata/mips/Makefile
@@ -0,0 +1,5 @@
+ifdef CONFIG_RISCV_ALTERNATIVE_EARLY
+CFLAGS_errata.o := -mcmodel=medany
+endif
+
+obj-y += errata.o
diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errata.c
new file mode 100644
index 0000000000000000000000000000000000000000..e984a8152208c34690f89d8101571b097485c360
--- /dev/null
+++ b/arch/riscv/errata/mips/errata.c
@@ -0,0 +1,67 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2025 MIPS.
+ */
+
+#include <linux/memory.h>
+#include <linux/module.h>
+#include <asm/text-patching.h>
+#include <asm/alternative.h>
+#include <asm/errata_list.h>
+#include <asm/vendorid_list.h>
+#include <asm/vendor_extensions.h>
+#include <asm/vendor_extensions/mips.h>
+
+static inline bool errata_probe_pause(void)
+{
+	if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE))
+		return false;
+
+	if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL))
+		return false;
+
+	return true;
+}
+
+static u32 mips_errata_probe(void)
+{
+	u32 cpu_req_errata = 0;
+
+	if (errata_probe_pause())
+		cpu_req_errata |= BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE);
+
+	return cpu_req_errata;
+}
+
+void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+			    unsigned long archid, unsigned long impid,
+			    unsigned int stage)
+{
+	struct alt_entry *alt;
+	u32 cpu_req_errata = mips_errata_probe();
+	u32 tmp;
+
+	BUILD_BUG_ON(ERRATA_MIPS_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
+
+	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
+		return;
+
+	for (alt = begin; alt < end; alt++) {
+		if (alt->vendor_id != MIPS_VENDOR_ID)
+			continue;
+
+		if (alt->patch_id >= ERRATA_MIPS_NUMBER) {
+			WARN(1, "MIPS errata id:%d not in kernel errata list\n",
+			     alt->patch_id);
+			continue;
+		}
+
+		tmp = (1U << alt->patch_id);
+		if (cpu_req_errata && tmp) {
+			mutex_lock(&text_mutex);
+			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
+					  alt->alt_len);
+			mutex_unlock(&text_mutex);
+		}
+	}
+}
diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
index 3c2b59b25017929df92b4e6741ac1a9308bfec54..bc3ada8190a9e7dc7d904aeb3174c78329e4d8d7 100644
--- a/arch/riscv/include/asm/alternative.h
+++ b/arch/riscv/include/asm/alternative.h
@@ -48,6 +48,9 @@ struct alt_entry {
 void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			     unsigned long archid, unsigned long impid,
 			     unsigned int stage);
+void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
+			      unsigned long archid, unsigned long impid,
+			      unsigned int stage);
 void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
 			      unsigned long archid, unsigned long impid,
 			      unsigned int stage);
diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
index 0b749e7102162477432f7cf9a34768fbdf2e8cc7..80bd52363c68690f33bfd54e0cc40399cd60b57b 100644
--- a/arch/riscv/include/asm/cmpxchg.h
+++ b/arch/riscv/include/asm/cmpxchg.h
@@ -14,6 +14,7 @@
 #include <asm/insn-def.h>
 #include <asm/cpufeature-macros.h>
 #include <asm/processor.h>
+#include <asm/errata_list.h>
 
 #define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append,		\
 			   swap_append, r, p, n)				\
@@ -438,7 +439,7 @@ static __always_inline void __cmpwait(volatile void *ptr,
 	return;
 
 no_zawrs:
-	asm volatile(RISCV_PAUSE : : : "memory");
+	ALT_RISCV_PAUSE();
 }
 
 #define __cmpwait_relaxed(ptr, val) \
diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
index 6e426ed7919a4acd997b60b723c0d5cfddb4cff6..618dee38d8d1347711fd46a459bfc8d2cb7bf42b 100644
--- a/arch/riscv/include/asm/errata_list.h
+++ b/arch/riscv/include/asm/errata_list.h
@@ -5,7 +5,6 @@
 #ifndef ASM_ERRATA_LIST_H
 #define ASM_ERRATA_LIST_H
 
-#include <asm/alternative.h>
 #include <asm/csr.h>
 #include <asm/insn-def.h>
 #include <asm/hwcap.h>
@@ -29,6 +28,11 @@
 #define	ERRATA_THEAD_NUMBER 3
 #endif
 
+#ifdef CONFIG_ERRATA_MIPS
+#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0
+#define ERRATA_MIPS_NUMBER 1
+#endif
+
 #ifdef __ASSEMBLY__
 
 #define ALT_INSN_FAULT(x)						\
@@ -59,6 +63,17 @@ asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID,	\
 		ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)	\
 		: : "r" (addr), "r" (asid) : "memory")
 
+#define ALT_RISCV_PAUSE()					\
+asm(ALTERNATIVE(	\
+		RISCV_PAUSE, /* Original RISC‑V pause insn */	\
+		".4byte 0x00501013", /* Replacement for MIPS P8700 */	\
+		MIPS_VENDOR_ID, /* Vendor ID to match */	\
+		ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */	\
+		CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)	\
+	: /* no outputs */	\
+	: /* no inputs */	\
+	: "memory")
+
 /*
  * _val is marked as "will be overwritten", so need to set it to 0
  * in the default case.
diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
index 8f383f05a290f123d941226b5dd975381d7d8536..8f749552ecfe6220bbc35f1c4677c6de8f7abdec 100644
--- a/arch/riscv/include/asm/vdso/processor.h
+++ b/arch/riscv/include/asm/vdso/processor.h
@@ -5,6 +5,8 @@
 #ifndef __ASSEMBLY__
 
 #include <asm/barrier.h>
+
+#include <asm/errata_list.h>
 #include <asm/insn-def.h>
 
 static inline void cpu_relax(void)
@@ -19,7 +21,7 @@ static inline void cpu_relax(void)
 	 * Reduce instruction retirement.
 	 * This assumes the PC changes.
 	 */
-	__asm__ __volatile__ (RISCV_PAUSE);
+	ALT_RISCV_PAUSE();
 	barrier();
 }
 
diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
index a5150cdf34d87f01baf6d3ef843bc2d6d8d54095..3b09874d7a6dfb8f8aa45b0be41c20711d539e78 100644
--- a/arch/riscv/include/asm/vendorid_list.h
+++ b/arch/riscv/include/asm/vendorid_list.h
@@ -9,5 +9,6 @@
 #define MICROCHIP_VENDOR_ID	0x029
 #define SIFIVE_VENDOR_ID	0x489
 #define THEAD_VENDOR_ID		0x5b7
+#define MIPS_VENDOR_ID		0x722
 
 #endif
diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
index 7eb3cb1215c62130c63a72fc650cddff6bae62af..7642704c7f1841f67fc23738063f22b4ecf58194 100644
--- a/arch/riscv/kernel/alternative.c
+++ b/arch/riscv/kernel/alternative.c
@@ -47,6 +47,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
 		cpu_mfr_info->patch_func = andes_errata_patch_func;
 		break;
 #endif
+#ifdef CONFIG_ERRATA_MIPS
+	case MIPS_VENDOR_ID:
+		cpu_mfr_info->patch_func = mips_errata_patch_func;
+		break;
+#endif
 #ifdef CONFIG_ERRATA_SIFIVE
 	case SIFIVE_VENDOR_ID:
 		cpu_mfr_info->patch_func = sifive_errata_patch_func;
diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
index 75656afa2d6be8ca5f2c4711455567c7f8fc0b97..b18373ed23d65df0dc828246269e9039bb0b0c6b 100644
--- a/arch/riscv/kernel/entry.S
+++ b/arch/riscv/kernel/entry.S
@@ -15,6 +15,8 @@
 #include <asm/thread_info.h>
 #include <asm/asm-offsets.h>
 #include <asm/errata_list.h>
+#include <asm/alternative.h>
+
 #include <linux/sizes.h>
 
 	.section .irqentry.text, "ax"
diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
index 8d0374d7ce8ed72320f58e4cea212d0e2bce8fd4..7ee95ebadc258a3a46e59698cd143266f6797a0c 100644
--- a/arch/riscv/mm/init.c
+++ b/arch/riscv/mm/init.c
@@ -33,6 +33,7 @@
 #include <asm/soc.h>
 #include <asm/sparsemem.h>
 #include <asm/tlbflush.h>
+#include <asm/alternative.h>
 
 #include "../kernel/head.h"
 

-- 
2.34.1

Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Andrew Jones]

On Wed, Jun 25, 2025 at 04:21:01PM +0200, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 
> Use the hwprobe syscall to decide which PAUSE instruction to execute in
> userspace code.
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>  tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
>  1 file changed, 17 insertions(+), 10 deletions(-)
> 
> diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
> index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
> --- a/tools/arch/riscv/include/asm/vdso/processor.h
> +++ b/tools/arch/riscv/include/asm/vdso/processor.h
> @@ -4,26 +4,33 @@
>  
>  #ifndef __ASSEMBLY__
>  
> +#include <asm/hwprobe.h>
> +#include <sys/hwprobe.h>
> +#include <asm/vendor/mips.h>
>  #include <asm-generic/barrier.h>
>  
>  static inline void cpu_relax(void)
>  {
> +	struct riscv_hwprobe pair;
> +	bool has_mipspause;
>  #ifdef __riscv_muldiv
>  	int dummy;
>  	/* In lieu of a halt instruction, induce a long-latency stall. */
>  	__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>  #endif
>  
> -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
> -	/*
> -	 * Reduce instruction retirement.
> -	 * This assumes the PC changes.
> -	 */
> -	__asm__ __volatile__ ("pause");
> -#else
> -	/* Encoding of the pause instruction */
> -	__asm__ __volatile__ (".4byte 0x100000F");
> -#endif
> +	pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
> +	__riscv_hwprobe(&pair, 1, 0, NULL, 0);
> +	has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
> +
> +	if (has_mipspause) {
> +		/* Encoding of the mips pause instruction */
> +		__asm__ __volatile__(".4byte 0x00501013");
> +	} else {
> +		/* Encoding of the pause instruction */
> +		__asm__ __volatile__(".4byte 0x100000F");
> +	}
> +

cpu_relax() is used in places where we cannot afford the overhead nor call
arbitrary functions which may take locks, etc. We've even had trouble
using a static key here in the past since this is inlined and it bloated
the size too much. You'll need to use ALTERNATIVE().

Thanks,
drew


>  	barrier();
>  }
>  
> 
> -- 
> 2.34.1
> 
> 
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Andrew Jones]

On Thu, Jun 26, 2025 at 11:21:10AM +0200, Andrew Jones wrote:
> On Wed, Jun 25, 2025 at 04:21:01PM +0200, Aleksa Paunovic via B4 Relay wrote:
> > From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> > 
> > Use the hwprobe syscall to decide which PAUSE instruction to execute in
> > userspace code.
> > 
> > Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> > ---
> >  tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
> >  1 file changed, 17 insertions(+), 10 deletions(-)
> > 
> > diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
> > index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
> > --- a/tools/arch/riscv/include/asm/vdso/processor.h
> > +++ b/tools/arch/riscv/include/asm/vdso/processor.h
> > @@ -4,26 +4,33 @@
> >  
> >  #ifndef __ASSEMBLY__
> >  
> > +#include <asm/hwprobe.h>
> > +#include <sys/hwprobe.h>
> > +#include <asm/vendor/mips.h>
> >  #include <asm-generic/barrier.h>
> >  
> >  static inline void cpu_relax(void)
> >  {
> > +	struct riscv_hwprobe pair;
> > +	bool has_mipspause;
> >  #ifdef __riscv_muldiv
> >  	int dummy;
> >  	/* In lieu of a halt instruction, induce a long-latency stall. */
> >  	__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
> >  #endif
> >  
> > -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
> > -	/*
> > -	 * Reduce instruction retirement.
> > -	 * This assumes the PC changes.
> > -	 */
> > -	__asm__ __volatile__ ("pause");
> > -#else
> > -	/* Encoding of the pause instruction */
> > -	__asm__ __volatile__ (".4byte 0x100000F");
> > -#endif
> > +	pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
> > +	__riscv_hwprobe(&pair, 1, 0, NULL, 0);
> > +	has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
> > +
> > +	if (has_mipspause) {
> > +		/* Encoding of the mips pause instruction */
> > +		__asm__ __volatile__(".4byte 0x00501013");
> > +	} else {
> > +		/* Encoding of the pause instruction */
> > +		__asm__ __volatile__(".4byte 0x100000F");
> > +	}
> > +
> 
> cpu_relax() is used in places where we cannot afford the overhead nor call
> arbitrary functions which may take locks, etc. We've even had trouble
> using a static key here in the past since this is inlined and it bloated
> the size too much. You'll need to use ALTERNATIVE().

Oh, I see now that the next patch is handling the kernel cpu_relax with
ALTERNATIVE and this was just the tools cpu_relax. We don't want to make
a syscall inside cpu_relax though either, since it gets called in loops.
It'd be better to just call the standard pause (0x100000F) even if it
does nothing. Or maybe there's some define that can be added/used to
select the correct instruction?

Thanks,
drew

Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Andrew Jones]

On Thu, Jun 26, 2025 at 11:34:21AM +0200, Andrew Jones wrote:
> On Thu, Jun 26, 2025 at 11:21:10AM +0200, Andrew Jones wrote:
> > On Wed, Jun 25, 2025 at 04:21:01PM +0200, Aleksa Paunovic via B4 Relay wrote:
> > > From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> > > 
> > > Use the hwprobe syscall to decide which PAUSE instruction to execute in
> > > userspace code.
> > > 
> > > Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> > > ---
> > >  tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
> > >  1 file changed, 17 insertions(+), 10 deletions(-)
> > > 
> > > diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
> > > index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
> > > --- a/tools/arch/riscv/include/asm/vdso/processor.h
> > > +++ b/tools/arch/riscv/include/asm/vdso/processor.h
> > > @@ -4,26 +4,33 @@
> > >  
> > >  #ifndef __ASSEMBLY__
> > >  
> > > +#include <asm/hwprobe.h>
> > > +#include <sys/hwprobe.h>
> > > +#include <asm/vendor/mips.h>
> > >  #include <asm-generic/barrier.h>
> > >  
> > >  static inline void cpu_relax(void)
> > >  {
> > > +	struct riscv_hwprobe pair;
> > > +	bool has_mipspause;
> > >  #ifdef __riscv_muldiv
> > >  	int dummy;
> > >  	/* In lieu of a halt instruction, induce a long-latency stall. */
> > >  	__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
> > >  #endif
> > >  
> > > -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
> > > -	/*
> > > -	 * Reduce instruction retirement.
> > > -	 * This assumes the PC changes.
> > > -	 */
> > > -	__asm__ __volatile__ ("pause");
> > > -#else
> > > -	/* Encoding of the pause instruction */
> > > -	__asm__ __volatile__ (".4byte 0x100000F");
> > > -#endif
> > > +	pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
> > > +	__riscv_hwprobe(&pair, 1, 0, NULL, 0);
> > > +	has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
> > > +
> > > +	if (has_mipspause) {
> > > +		/* Encoding of the mips pause instruction */
> > > +		__asm__ __volatile__(".4byte 0x00501013");
> > > +	} else {
> > > +		/* Encoding of the pause instruction */
> > > +		__asm__ __volatile__(".4byte 0x100000F");
> > > +	}
> > > +
> > 
> > cpu_relax() is used in places where we cannot afford the overhead nor call
> > arbitrary functions which may take locks, etc. We've even had trouble
> > using a static key here in the past since this is inlined and it bloated
> > the size too much. You'll need to use ALTERNATIVE().
> 
> Oh, I see now that the next patch is handling the kernel cpu_relax with
> ALTERNATIVE and this was just the tools cpu_relax. We don't want to make
> a syscall inside cpu_relax though either, since it gets called in loops.

(Another follow up to myself...)

I guess with the vdso cached result it should only be a handful of
instructions, but it still seems odd to embed a call in cpu_relax.

Thanks,
drew

> It'd be better to just call the standard pause (0x100000F) even if it
> does nothing. Or maybe there's some define that can be added/used to
> select the correct instruction?
> 
> Thanks,
> drew

Re: [PATCH v4 1/7] dt-bindings: riscv: Add xmipsexectl ISA extension description

[Conor Dooley]

[-- Attachment #1: Type: text/plain, Size: 1571 bytes --]

On Wed, Jun 25, 2025 at 04:20:56PM +0200, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> 
> The xmipsexectl extension is described in the MIPS RV64 P8700/P8700-F
> Multiprocessing System Programmer’s Guide linked at [1].
> 
> Link: https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf
> 
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>  Documentation/devicetree/bindings/riscv/extensions.yaml | 6 ++++++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
> index ede6a58ccf5347d92785dc085a011052c1aade14..de41a6f074d3af2ceaf5293dfe75d16f43d416d6 100644
> --- a/Documentation/devicetree/bindings/riscv/extensions.yaml
> +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
> @@ -662,6 +662,12 @@ properties:
>              Registers in the AX45MP datasheet.
>              https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
>  
> +        # MIPS
> +        - const: xmipsexectl
> +          description:
> +            The MIPS extension for execution control as documented in
> +            https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf

Acked-by: Conor Dooley <conor.dooley@microchip.com>

> +
>          # SiFive
>          - const: xsfvqmaccdod
>            description:
> 
> -- 
> 2.34.1
> 
> 
> 

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]

Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Aleksa Paunovic]

On 26. 6. 25. 12:49, Andrew Jones wrote:> On Thu, Jun 26, 2025 at 11:34:21AM +0200, Andrew Jones wrote:
>> On Thu, Jun 26, 2025 at 11:21:10AM +0200, Andrew Jones wrote:
>>> On Wed, Jun 25, 2025 at 04:21:01PM +0200, Aleksa Paunovic via B4 Relay wrote:
>>>> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>>>
>>>> Use the hwprobe syscall to decide which PAUSE instruction to execute in
>>>> userspace code.
>>>>
>>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>>> ---
>>>>  tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
>>>>  1 file changed, 17 insertions(+), 10 deletions(-)
>>>>
>>>> diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
>>>> index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
>>>> --- a/tools/arch/riscv/include/asm/vdso/processor.h
>>>> +++ b/tools/arch/riscv/include/asm/vdso/processor.h
>>>> @@ -4,26 +4,33 @@
>>>>
>>>>  #ifndef __ASSEMBLY__
>>>>
>>>> +#include <asm/hwprobe.h>
>>>> +#include <sys/hwprobe.h>
>>>> +#include <asm/vendor/mips.h>
>>>>  #include <asm-generic/barrier.h>
>>>>
>>>>  static inline void cpu_relax(void)
>>>>  {
>>>> + struct riscv_hwprobe pair;
>>>> + bool has_mipspause;
>>>>  #ifdef __riscv_muldiv
>>>>   int dummy;
>>>>   /* In lieu of a halt instruction, induce a long-latency stall. */
>>>>   __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>>>>  #endif
>>>>
>>>> -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
>>>> - /*
>>>> -  * Reduce instruction retirement.
>>>> -  * This assumes the PC changes.
>>>> -  */
>>>> - __asm__ __volatile__ ("pause");
>>>> -#else
>>>> - /* Encoding of the pause instruction */
>>>> - __asm__ __volatile__ (".4byte 0x100000F");
>>>> -#endif
>>>> + pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
>>>> + __riscv_hwprobe(&pair, 1, 0, NULL, 0);
>>>> + has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
>>>> +
>>>> + if (has_mipspause) {
>>>> +         /* Encoding of the mips pause instruction */
>>>> +         __asm__ __volatile__(".4byte 0x00501013");
>>>> + } else {
>>>> +         /* Encoding of the pause instruction */
>>>> +         __asm__ __volatile__(".4byte 0x100000F");
>>>> + }
>>>> +
>>>
>>> cpu_relax() is used in places where we cannot afford the overhead nor call
>>> arbitrary functions which may take locks, etc. We've even had trouble
>>> using a static key here in the past since this is inlined and it bloated
>>> the size too much. You'll need to use ALTERNATIVE().
>>
>> Oh, I see now that the next patch is handling the kernel cpu_relax with
>> ALTERNATIVE and this was just the tools cpu_relax. We don't want to make
>> a syscall inside cpu_relax though either, since it gets called in loops.
> 
> (Another follow up to myself...)
> 
> I guess with the vdso cached result it should only be a handful of
> instructions, but it still seems odd to embed a call in cpu_relax.
>
  
Hi Andrew,

Thank you for your comments!

> Thanks,
> drew
> 
>> It'd be better to just call the standard pause (0x100000F) even if it
>> does nothing. Or maybe there's some define that can be added/used to
>> select the correct instruction?
>>

We did try using an ifdef/else in v3, but since that would have to be marked
non-portable, we decided to go with a hwprobe call. 
Since the MIPS pause should behave as a nop on other CPUs,
would leaving both the standard pause and the MIPS pause calls be an acceptable solution?

That said, I am not sure how this would behave on future MIPS CPUs in case they support both encodings.

Best regards,
Aleksa

>> Thanks,
>> drew

Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Andrew Jones]

On Fri, Jun 27, 2025 at 08:40:53AM +0000, Aleksa Paunovic wrote:
> On 26. 6. 25. 12:49, Andrew Jones wrote:> On Thu, Jun 26, 2025 at 11:34:21AM +0200, Andrew Jones wrote:
> >> On Thu, Jun 26, 2025 at 11:21:10AM +0200, Andrew Jones wrote:
> >>> On Wed, Jun 25, 2025 at 04:21:01PM +0200, Aleksa Paunovic via B4 Relay wrote:
> >>>> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> >>>>
> >>>> Use the hwprobe syscall to decide which PAUSE instruction to execute in
> >>>> userspace code.
> >>>>
> >>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> >>>> ---
> >>>>  tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
> >>>>  1 file changed, 17 insertions(+), 10 deletions(-)
> >>>>
> >>>> diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
> >>>> index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
> >>>> --- a/tools/arch/riscv/include/asm/vdso/processor.h
> >>>> +++ b/tools/arch/riscv/include/asm/vdso/processor.h
> >>>> @@ -4,26 +4,33 @@
> >>>>
> >>>>  #ifndef __ASSEMBLY__
> >>>>
> >>>> +#include <asm/hwprobe.h>
> >>>> +#include <sys/hwprobe.h>
> >>>> +#include <asm/vendor/mips.h>
> >>>>  #include <asm-generic/barrier.h>
> >>>>
> >>>>  static inline void cpu_relax(void)
> >>>>  {
> >>>> + struct riscv_hwprobe pair;
> >>>> + bool has_mipspause;
> >>>>  #ifdef __riscv_muldiv
> >>>>   int dummy;
> >>>>   /* In lieu of a halt instruction, induce a long-latency stall. */
> >>>>   __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
> >>>>  #endif
> >>>>
> >>>> -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
> >>>> - /*
> >>>> -  * Reduce instruction retirement.
> >>>> -  * This assumes the PC changes.
> >>>> -  */
> >>>> - __asm__ __volatile__ ("pause");
> >>>> -#else
> >>>> - /* Encoding of the pause instruction */
> >>>> - __asm__ __volatile__ (".4byte 0x100000F");
> >>>> -#endif
> >>>> + pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
> >>>> + __riscv_hwprobe(&pair, 1, 0, NULL, 0);
> >>>> + has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
> >>>> +
> >>>> + if (has_mipspause) {
> >>>> +         /* Encoding of the mips pause instruction */
> >>>> +         __asm__ __volatile__(".4byte 0x00501013");
> >>>> + } else {
> >>>> +         /* Encoding of the pause instruction */
> >>>> +         __asm__ __volatile__(".4byte 0x100000F");
> >>>> + }
> >>>> +
> >>>
> >>> cpu_relax() is used in places where we cannot afford the overhead nor call
> >>> arbitrary functions which may take locks, etc. We've even had trouble
> >>> using a static key here in the past since this is inlined and it bloated
> >>> the size too much. You'll need to use ALTERNATIVE().
> >>
> >> Oh, I see now that the next patch is handling the kernel cpu_relax with
> >> ALTERNATIVE and this was just the tools cpu_relax. We don't want to make
> >> a syscall inside cpu_relax though either, since it gets called in loops.
> > 
> > (Another follow up to myself...)
> > 
> > I guess with the vdso cached result it should only be a handful of
> > instructions, but it still seems odd to embed a call in cpu_relax.
> >
>   
> Hi Andrew,
> 
> Thank you for your comments!
> 
> > Thanks,
> > drew
> > 
> >> It'd be better to just call the standard pause (0x100000F) even if it
> >> does nothing. Or maybe there's some define that can be added/used to
> >> select the correct instruction?
> >>
> 
> We did try using an ifdef/else in v3, but since that would have to be marked
> non-portable, we decided to go with a hwprobe call. 
> Since the MIPS pause should behave as a nop on other CPUs,
> would leaving both the standard pause and the MIPS pause calls be an acceptable solution?
> 
> That said, I am not sure how this would behave on future MIPS CPUs in case they support both encodings.

We should probably avoid assuming that undefined custom instructions will
behave as nops everywhere, meaning it should remain guarded. This seems
like a problem we should try to solve before we get even more pause
instructions or whatever that need dynamic selection in userspace, but I
can't think of anything reasonable atm. For now, we may need to live with
vdso hwprobe calls in places like cpu_relax. I'll stop complaining about
this patch as I can't think of anything better.

Thanks,
drew

> 
> Best regards,
> Aleksa
> 
> >> Thanks,
> >> drew

Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Aleksa Paunovic]

On 27. 6. 25. 13:08, Andrew Jones wrote:> On Fri, Jun 27, 2025 at 08:40:53AM +0000, Aleksa Paunovic wrote:
>> On 26. 6. 25. 12:49, Andrew Jones wrote:> On Thu, Jun 26, 2025 at 11:34:21AM +0200, Andrew Jones wrote:
>>>> On Thu, Jun 26, 2025 at 11:21:10AM +0200, Andrew Jones wrote:
>>>>> On Wed, Jun 25, 2025 at 04:21:01PM +0200, Aleksa Paunovic via B4 Relay wrote:
>>>>>> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>>>>>
>>>>>> Use the hwprobe syscall to decide which PAUSE instruction to execute in
>>>>>> userspace code.
>>>>>>
>>>>>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>>>>>> ---
>>>>>>  tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
>>>>>>  1 file changed, 17 insertions(+), 10 deletions(-)
>>>>>>
>>>>>> diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
>>>>>> index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
>>>>>> --- a/tools/arch/riscv/include/asm/vdso/processor.h
>>>>>> +++ b/tools/arch/riscv/include/asm/vdso/processor.h
>>>>>> @@ -4,26 +4,33 @@
>>>>>>
>>>>>>  #ifndef __ASSEMBLY__
>>>>>>
>>>>>> +#include <asm/hwprobe.h>
>>>>>> +#include <sys/hwprobe.h>
>>>>>> +#include <asm/vendor/mips.h>
>>>>>>  #include <asm-generic/barrier.h>
>>>>>>
>>>>>>  static inline void cpu_relax(void)
>>>>>>  {
>>>>>> + struct riscv_hwprobe pair;
>>>>>> + bool has_mipspause;
>>>>>>  #ifdef __riscv_muldiv
>>>>>>   int dummy;
>>>>>>   /* In lieu of a halt instruction, induce a long-latency stall. */
>>>>>>   __asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>>>>>>  #endif
>>>>>>
>>>>>> -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
>>>>>> - /*
>>>>>> -  * Reduce instruction retirement.
>>>>>> -  * This assumes the PC changes.
>>>>>> -  */
>>>>>> - __asm__ __volatile__ ("pause");
>>>>>> -#else
>>>>>> - /* Encoding of the pause instruction */
>>>>>> - __asm__ __volatile__ (".4byte 0x100000F");
>>>>>> -#endif
>>>>>> + pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
>>>>>> + __riscv_hwprobe(&pair, 1, 0, NULL, 0);
>>>>>> + has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
>>>>>> +
>>>>>> + if (has_mipspause) {
>>>>>> +         /* Encoding of the mips pause instruction */
>>>>>> +         __asm__ __volatile__(".4byte 0x00501013");
>>>>>> + } else {
>>>>>> +         /* Encoding of the pause instruction */
>>>>>> +         __asm__ __volatile__(".4byte 0x100000F");
>>>>>> + }
>>>>>> +
>>>>>
>>>>> cpu_relax() is used in places where we cannot afford the overhead nor call
>>>>> arbitrary functions which may take locks, etc. We've even had trouble
>>>>> using a static key here in the past since this is inlined and it bloated
>>>>> the size too much. You'll need to use ALTERNATIVE().
>>>>
>>>> Oh, I see now that the next patch is handling the kernel cpu_relax with
>>>> ALTERNATIVE and this was just the tools cpu_relax. We don't want to make
>>>> a syscall inside cpu_relax though either, since it gets called in loops.
>>>
>>> (Another follow up to myself...)
>>>
>>> I guess with the vdso cached result it should only be a handful of
>>> instructions, but it still seems odd to embed a call in cpu_relax.
>>>
>>
>> Hi Andrew,
>>
>> Thank you for your comments!
>>
>>> Thanks,
>>> drew
>>>
>>>> It'd be better to just call the standard pause (0x100000F) even if it
>>>> does nothing. Or maybe there's some define that can be added/used to
>>>> select the correct instruction?
>>>>
>>
>> We did try using an ifdef/else in v3, but since that would have to be marked
>> non-portable, we decided to go with a hwprobe call.
>> Since the MIPS pause should behave as a nop on other CPUs,
>> would leaving both the standard pause and the MIPS pause calls be an acceptable solution?
>>
>> That said, I am not sure how this would behave on future MIPS CPUs in case they support both encodings.
> 
> We should probably avoid assuming that undefined custom instructions will
> behave as nops everywhere, meaning it should remain guarded. This seems
> like a problem we should try to solve before we get even more pause
> instructions or whatever that need dynamic selection in userspace, but I
> can't think of anything reasonable atm. For now, we may need to live with
> vdso hwprobe calls in places like cpu_relax. I'll stop complaining about
> this patch as I can't think of anything better.
> 

Hi Andrew,

Thank you again for your response. 
 
We talked in an internal meeting and we would be fine with not touching the userspace
code with this series (just deleting this particular patch), 
if that's a more acceptable solution. I am not sure how else we could proceed?

I am CCing the others who participated in the earlier conversations.

Best regards,
Aleksa

> Thanks,
> drew
> 
>>
>> Best regards,
>> Aleksa
>>
>>>> Thanks,
>>>> drew

Re: [PATCH v4 2/7] riscv: Add xmipsexectl as a vendor extension

[Alexandre Ghiti]

Hi Aleksa,

On 6/25/25 16:20, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Add support for MIPS vendor extensions. Add support for the xmipsexectl
> vendor extension.
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   arch/riscv/Kconfig.vendor                       | 13 +++++++++++++
>   arch/riscv/include/asm/vendor_extensions/mips.h | 16 ++++++++++++++++
>   arch/riscv/kernel/vendor_extensions.c           | 10 ++++++++++
>   arch/riscv/kernel/vendor_extensions/Makefile    |  1 +
>   arch/riscv/kernel/vendor_extensions/mips.c      | 22 ++++++++++++++++++++++
>   5 files changed, 62 insertions(+)
>
> diff --git a/arch/riscv/Kconfig.vendor b/arch/riscv/Kconfig.vendor
> index e14f26368963c178e3271e0f716b27fff7671e78..3c1f92e406c3f21481b56e61229716fd02ab81b2 100644
> --- a/arch/riscv/Kconfig.vendor
> +++ b/arch/riscv/Kconfig.vendor
> @@ -16,6 +16,19 @@ config RISCV_ISA_VENDOR_EXT_ANDES
>   	  If you don't know what to do here, say Y.
>   endmenu
>   
> +menu "MIPS"
> +config RISCV_ISA_VENDOR_EXT_MIPS
> +	bool "MIPS vendor extension support"
> +	select RISCV_ISA_VENDOR_EXT
> +	default y
> +	help
> +	  Say N here to disable detection of and support for all MIPS vendor
> +	  extensions. Without this option enabled, MIPS vendor extensions will
> +	  not be detected at boot and their presence not reported to userspace.
> +
> +	  If you don't know what to do here, say Y.
> +endmenu
> +
>   menu "SiFive"
>   config RISCV_ISA_VENDOR_EXT_SIFIVE
>   	bool "SiFive vendor extension support"
> diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..757c941cfd86e9fced6169b1a82200e6bb5c6132
> --- /dev/null
> +++ b/arch/riscv/include/asm/vendor_extensions/mips.h
> @@ -0,0 +1,16 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2025 MIPS.
> + */
> +
> +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
> +#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
> +
> +#include <asm/vendor_extensions.h>
> +#include <linux/types.h>
> +
> +#define RISCV_ISA_VENDOR_EXT_XMIPSEXECTL	0
> +
> +extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
> +
> +#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
> diff --git a/arch/riscv/kernel/vendor_extensions.c b/arch/riscv/kernel/vendor_extensions.c
> index 92d8ff81f42c9ceba63bef0170ab134564a24a4e..bb4a7592368560ebacbcd8a5ce335eea6312ea5c 100644
> --- a/arch/riscv/kernel/vendor_extensions.c
> +++ b/arch/riscv/kernel/vendor_extensions.c
> @@ -6,6 +6,7 @@
>   #include <asm/vendorid_list.h>
>   #include <asm/vendor_extensions.h>
>   #include <asm/vendor_extensions/andes.h>
> +#include <asm/vendor_extensions/mips.h>
>   #include <asm/vendor_extensions/sifive.h>
>   #include <asm/vendor_extensions/thead.h>
>   
> @@ -16,6 +17,9 @@ struct riscv_isa_vendor_ext_data_list *riscv_isa_vendor_ext_list[] = {
>   #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_ANDES
>   	&riscv_isa_vendor_ext_list_andes,
>   #endif
> +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
> +	&riscv_isa_vendor_ext_list_mips,
> +#endif
>   #ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
>   	&riscv_isa_vendor_ext_list_sifive,
>   #endif
> @@ -49,6 +53,12 @@ bool __riscv_isa_vendor_extension_available(int cpu, unsigned long vendor, unsig
>   		cpu_bmap = riscv_isa_vendor_ext_list_andes.per_hart_isa_bitmap;
>   		break;
>   	#endif
> +	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
> +	case MIPS_VENDOR_ID:
> +		bmap = &riscv_isa_vendor_ext_list_mips.all_harts_isa_bitmap;
> +		cpu_bmap = riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap;
> +		break;
> +	#endif
>   	#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE
>   	case SIFIVE_VENDOR_ID:
>   		bmap = &riscv_isa_vendor_ext_list_sifive.all_harts_isa_bitmap;
> diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
> index a4eca96d1c8a2fd165220f6439a3884cf90a9593..ccad4ebafb43412e72e654da3bdb9face53b80c6 100644
> --- a/arch/riscv/kernel/vendor_extensions/Makefile
> +++ b/arch/riscv/kernel/vendor_extensions/Makefile
> @@ -1,6 +1,7 @@
>   # SPDX-License-Identifier: GPL-2.0-only
>   
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o
> +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips.o
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive.o
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive_hwprobe.o
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o
> diff --git a/arch/riscv/kernel/vendor_extensions/mips.c b/arch/riscv/kernel/vendor_extensions/mips.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..f691129f96c21f2ef089124f4b64a6f0a8e6d4aa
> --- /dev/null
> +++ b/arch/riscv/kernel/vendor_extensions/mips.c
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2025 MIPS.
> + */
> +
> +#include <asm/cpufeature.h>
> +#include <asm/vendor_extensions.h>
> +#include <asm/vendor_extensions/mips.h>
> +
> +#include <linux/array_size.h>
> +#include <linux/cpumask.h>
> +#include <linux/types.h>
> +
> +/* All MIPS vendor extensions supported in Linux */
> +static const struct riscv_isa_ext_data riscv_isa_vendor_ext_mips[] = {
> +	__RISCV_ISA_EXT_DATA(xmipsexectl, RISCV_ISA_VENDOR_EXT_XMIPSEXECTL),
> +};
> +
> +struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips = {
> +	.ext_data_count = ARRAY_SIZE(riscv_isa_vendor_ext_mips),
> +	.ext_data = riscv_isa_vendor_ext_mips,
> +};


Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex

Re: [PATCH v4 3/7] riscv: Add xmipsexectl PAUSE instruction

[Alexandre Ghiti]

On 6/25/25 16:20, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Add MIPS.PAUSE instruction opcode. This instruction is a part of the
> xmipsexectl vendor extension.
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   arch/riscv/include/asm/vendor_extensions/mips.h | 7 +++++++
>   1 file changed, 7 insertions(+)
>
> diff --git a/arch/riscv/include/asm/vendor_extensions/mips.h b/arch/riscv/include/asm/vendor_extensions/mips.h
> index 757c941cfd86e9fced6169b1a82200e6bb5c6132..f8eca0bcf53e2de1bbdc66821fe95987105ed85a 100644
> --- a/arch/riscv/include/asm/vendor_extensions/mips.h
> +++ b/arch/riscv/include/asm/vendor_extensions/mips.h
> @@ -13,4 +13,11 @@
>   
>   extern struct riscv_isa_vendor_ext_data_list riscv_isa_vendor_ext_list_mips;
>   
> +/* MIPS.PAUSE is an alternative opcode which is implemented to have the */
> +/* same behavior as PAUSE on some MIPS RISCV cores. */
> +/* It is a ‘hint’ encoding of the SLLI instruction, */
> +/* with rd = 0, rs1 = 0 and imm = 5. */


The comment block should have been like this:

/*
  * ...
  */


> +
> +#define MIPS_PAUSE	".4byte 0x00501013\n\t"
> +
>   #endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_H
>

Unless there is something else to change in the following patches, no 
need to resend the whole patchset just to fix the comment block, I'll do 
it when I merge it.

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex

Re: [PATCH v4 4/7] riscv: hwprobe: Add MIPS vendor extension probing

[Alexandre Ghiti]

On 6/25/25 16:20, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Add a new hwprobe key "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" which allows
> userspace to probe for the new xmipsexectl vendor extension.
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   arch/riscv/include/asm/hwprobe.h                   |  3 ++-
>   .../include/asm/vendor_extensions/mips_hwprobe.h   | 23 ++++++++++++++++++++++
>   arch/riscv/include/uapi/asm/hwprobe.h              |  1 +
>   arch/riscv/include/uapi/asm/vendor/mips.h          |  3 +++
>   arch/riscv/kernel/sys_hwprobe.c                    |  4 ++++
>   arch/riscv/kernel/vendor_extensions/Makefile       |  1 +
>   arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 22 +++++++++++++++++++++
>   7 files changed, 56 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/include/asm/hwprobe.h b/arch/riscv/include/asm/hwprobe.h
> index 7fe0a379474ae2c64d300d6fee4a012173f6a6d7..948d2b34e94e84e4c2c351ffe91f4b3afcefc3f7 100644
> --- a/arch/riscv/include/asm/hwprobe.h
> +++ b/arch/riscv/include/asm/hwprobe.h
> @@ -8,7 +8,7 @@
>   
>   #include <uapi/asm/hwprobe.h>
>   
> -#define RISCV_HWPROBE_MAX_KEY 13
> +#define RISCV_HWPROBE_MAX_KEY 14
>   
>   static inline bool riscv_hwprobe_key_is_valid(__s64 key)
>   {
> @@ -22,6 +22,7 @@ static inline bool hwprobe_key_is_bitmask(__s64 key)
>   	case RISCV_HWPROBE_KEY_IMA_EXT_0:
>   	case RISCV_HWPROBE_KEY_CPUPERF_0:
>   	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
> +	case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
>   	case RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0:
>   		return true;
>   	}
> diff --git a/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h b/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..0af8c07c22f293b5f772709f774de78dd60c7f39
> --- /dev/null
> +++ b/arch/riscv/include/asm/vendor_extensions/mips_hwprobe.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (C) 2025 MIPS.
> + */
> +
> +#ifndef _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
> +#define _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
> +
> +#include <linux/cpumask.h>
> +#include <uapi/asm/hwprobe.h>
> +
> +


2 newlines here ^


> +#ifdef CONFIG_RISCV_ISA_VENDOR_EXT_MIPS
> +void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair, const struct cpumask *cpus);
> +#else
> +static inline void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
> +						 const struct cpumask *cpus)
> +{
> +	pair->value = 0;
> +}
> +#endif
> +
> +#endif // _ASM_RISCV_VENDOR_EXTENSIONS_MIPS_HWPROBE_H_
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index aaf6ad97049931381f9542bb9316c873ec6ab9f6..5d30a4fae37a82ef4d968d20b187420772ad8946 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -106,6 +106,7 @@ struct riscv_hwprobe {
>   #define RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0	11
>   #define RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE	12
>   #define RISCV_HWPROBE_KEY_VENDOR_EXT_SIFIVE_0	13
> +#define RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0	14
>   /* Increase RISCV_HWPROBE_MAX_KEY when adding items. */
>   
>   /* Flags */
> diff --git a/arch/riscv/include/uapi/asm/vendor/mips.h b/arch/riscv/include/uapi/asm/vendor/mips.h
> new file mode 100644
> index 0000000000000000000000000000000000000000..11d41651178233a5f06ab9541ea0506d9883aa19
> --- /dev/null
> +++ b/arch/riscv/include/uapi/asm/vendor/mips.h
> @@ -0,0 +1,3 @@
> +/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
> +
> +#define RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL	(1 << 0)
> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
> index 0b170e18a2beba576f4f8787d6ef6aa67c5c3d0e..6c73e167ef4ccc7f99dd2793acde2595fffdcbad 100644
> --- a/arch/riscv/kernel/sys_hwprobe.c
> +++ b/arch/riscv/kernel/sys_hwprobe.c
> @@ -15,6 +15,7 @@
>   #include <asm/uaccess.h>
>   #include <asm/unistd.h>
>   #include <asm/vector.h>
> +#include <asm/vendor_extensions/mips_hwprobe.h>
>   #include <asm/vendor_extensions/sifive_hwprobe.h>
>   #include <asm/vendor_extensions/thead_hwprobe.h>
>   #include <vdso/vsyscall.h>
> @@ -309,6 +310,9 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>   	case RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0:
>   		hwprobe_isa_vendor_ext_thead_0(pair, cpus);
>   		break;
> +	case RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0:
> +		hwprobe_isa_vendor_ext_mips_0(pair, cpus);
> +		break;
>   
>   	/*
>   	 * For forward compatibility, unknown keys don't fail the whole
> diff --git a/arch/riscv/kernel/vendor_extensions/Makefile b/arch/riscv/kernel/vendor_extensions/Makefile
> index ccad4ebafb43412e72e654da3bdb9face53b80c6..bf116c82b6bdb3aee23e27fc0b2a69be7c7a5ccb 100644
> --- a/arch/riscv/kernel/vendor_extensions/Makefile
> +++ b/arch/riscv/kernel/vendor_extensions/Makefile
> @@ -2,6 +2,7 @@
>   
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_ANDES)	+= andes.o
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips.o
> +obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_MIPS)  	+= mips_hwprobe.o
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive.o
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_SIFIVE)	+= sifive_hwprobe.o
>   obj-$(CONFIG_RISCV_ISA_VENDOR_EXT_THEAD)	+= thead.o
> diff --git a/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c b/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..43944f2b484af257fa358cda53c12b4d6f54b78b
> --- /dev/null
> +++ b/arch/riscv/kernel/vendor_extensions/mips_hwprobe.c
> @@ -0,0 +1,22 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2025 MIPS.
> + */
> +
> +#include <asm/vendor_extensions/mips.h>
> +#include <asm/vendor_extensions/mips_hwprobe.h>
> +#include <asm/vendor_extensions/vendor_hwprobe.h>
> +
> +#include <linux/cpumask.h>
> +#include <linux/types.h>
> +
> +#include <uapi/asm/hwprobe.h>
> +#include <uapi/asm/vendor/mips.h>
> +
> +void hwprobe_isa_vendor_ext_mips_0(struct riscv_hwprobe *pair,
> +				   const struct cpumask *cpus)
> +{
> +	VENDOR_EXTENSION_SUPPORTED(
> +		pair, cpus, riscv_isa_vendor_ext_list_mips.per_hart_isa_bitmap,
> +		{ VENDOR_EXT_KEY(XMIPSEXECTL); });
> +}


I'll remove the superfluous newline when merging the patchset:

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex

Re: [PATCH v4 5/7] riscv: hwprobe: Document MIPS xmipsexectl vendor extension

[Alexandre Ghiti]

On 6/25/25 16:21, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Document support for MIPS vendor extensions using the key
> "RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0" and xmipsexectl vendor extension
> using the key "RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL".
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   Documentation/arch/riscv/hwprobe.rst | 9 +++++++++
>   1 file changed, 9 insertions(+)
>
> diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst
> index 2aa9be272d5de1c15559a978a956bc36c34de81c..2f449c9b15bdd6b9813c9a968deca1a4c4ff9b14 100644
> --- a/Documentation/arch/riscv/hwprobe.rst
> +++ b/Documentation/arch/riscv/hwprobe.rst
> @@ -327,6 +327,15 @@ The following keys are defined:
>     * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are
>       not supported at all and will generate a misaligned address fault.
>   
> +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the
> +  mips vendor extensions that are compatible with the
> +  :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
> +
> +  * MIPS
> +
> +    * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor
> +        extension is supported in the MIPS ISA extensions spec.
> +
>   * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the
>     thead vendor extensions that are compatible with the
>     :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
>

FWIW, just a note that in the documentation you mentioned in patch 1, 
xmipsexectl extension also provides 2 barrier instructions that are not 
implemented in this patchset.

Anyway:

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex

Re: [PATCH v4 6/7] riscv: Add tools support for xmipsexectl

[Alexandre Ghiti]

On 6/25/25 16:21, Aleksa Paunovic via B4 Relay wrote:
> From: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>
> Use the hwprobe syscall to decide which PAUSE instruction to execute in
> userspace code.
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   tools/arch/riscv/include/asm/vdso/processor.h | 27 +++++++++++++++++----------
>   1 file changed, 17 insertions(+), 10 deletions(-)
>
> diff --git a/tools/arch/riscv/include/asm/vdso/processor.h b/tools/arch/riscv/include/asm/vdso/processor.h
> index 662aca03984817f9c69186658b19e9dad9e4771c..027219a486b7b93814888190f8224af29498707c 100644
> --- a/tools/arch/riscv/include/asm/vdso/processor.h
> +++ b/tools/arch/riscv/include/asm/vdso/processor.h
> @@ -4,26 +4,33 @@
>   
>   #ifndef __ASSEMBLY__
>   
> +#include <asm/hwprobe.h>
> +#include <sys/hwprobe.h>
> +#include <asm/vendor/mips.h>
>   #include <asm-generic/barrier.h>
>   
>   static inline void cpu_relax(void)
>   {
> +	struct riscv_hwprobe pair;
> +	bool has_mipspause;
>   #ifdef __riscv_muldiv
>   	int dummy;
>   	/* In lieu of a halt instruction, induce a long-latency stall. */
>   	__asm__ __volatile__ ("div %0, %0, zero" : "=r" (dummy));
>   #endif
>   
> -#ifdef CONFIG_TOOLCHAIN_HAS_ZIHINTPAUSE
> -	/*
> -	 * Reduce instruction retirement.
> -	 * This assumes the PC changes.
> -	 */
> -	__asm__ __volatile__ ("pause");
> -#else
> -	/* Encoding of the pause instruction */
> -	__asm__ __volatile__ (".4byte 0x100000F");
> -#endif
> +	pair.key = RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0;
> +	__riscv_hwprobe(&pair, 1, 0, NULL, 0);


So this should not trigger a syscall, so even if it's weird, I guess 
that's ok.

Another solution that was already suggested for CFI would be to 
implement VDSO alternatives, we could easily parse the VDSO elf and 
patch it at boot time, I'm pretty sure that will be useful at some point.


> +	has_mipspause = pair.value & RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL;
> +
> +	if (has_mipspause) {
> +		/* Encoding of the mips pause instruction */
> +		__asm__ __volatile__(".4byte 0x00501013");


Here you could have used the MIPS_PAUSE introduced earlier.


> +	} else {
> +		/* Encoding of the pause instruction */
> +		__asm__ __volatile__(".4byte 0x100000F");
> +	}
> +
>   	barrier();
>   }
>   
>

Anyway, let's merge this for now:

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex

Re: [PATCH v4 7/7] riscv: errata: Fix the PAUSE Opcode for MIPS P8700

[Alexandre Ghiti]

On 6/25/25 16:21, Aleksa Paunovic via B4 Relay wrote:
> From: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>
> Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.
> Handle errata for the MIPS PAUSE instruction.
>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
> Signed-off-by: Raj Vishwanathan4 <rvishwanathan@mips.com>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
>   arch/riscv/Kconfig.errata               | 23 +++++++++++
>   arch/riscv/errata/Makefile              |  1 +
>   arch/riscv/errata/mips/Makefile         |  5 +++
>   arch/riscv/errata/mips/errata.c         | 67 +++++++++++++++++++++++++++++++++
>   arch/riscv/include/asm/alternative.h    |  3 ++
>   arch/riscv/include/asm/cmpxchg.h        |  3 +-
>   arch/riscv/include/asm/errata_list.h    | 17 ++++++++-
>   arch/riscv/include/asm/vdso/processor.h |  4 +-
>   arch/riscv/include/asm/vendorid_list.h  |  1 +
>   arch/riscv/kernel/alternative.c         |  5 +++
>   arch/riscv/kernel/entry.S               |  2 +
>   arch/riscv/mm/init.c                    |  1 +
>   12 files changed, 129 insertions(+), 3 deletions(-)
>
> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> index e318119d570de0acc0850a2e1a2505ecb71bea08..aca9b0cfcfecf91d4d1910f294ee109ed15f2d6c 100644
> --- a/arch/riscv/Kconfig.errata
> +++ b/arch/riscv/Kconfig.errata
> @@ -21,6 +21,29 @@ config ERRATA_ANDES_CMO
>   
>   	  If you don't know what to do here, say "Y".
>   
> +config ERRATA_MIPS
> +	bool "MIPS errata"
> +	depends on RISCV_ALTERNATIVE
> +	help
> +	  All MIPS errata Kconfig depend on this Kconfig. Disabling
> +	  this Kconfig will disable all MIPS errata. Please say "Y"
> +	  here if your platform uses MIPS CPU cores.
> +
> +	  Otherwise, please say "N" here to avoid unnecessary overhead.
> +
> +config ERRATA_MIPS_P8700_PAUSE_OPCODE
> +	bool "Fix the PAUSE Opcode for MIPS P8700"
> +	depends on ERRATA_MIPS && 64BIT
> +	default n
> +	help
> +	   The RISCV MIPS P8700 uses a different opcode for PAUSE.
> +	   It is a 'hint' encoding of the SLLI instruction,
> +	   with rd=0, rs1=0 and imm=5. It will behave as a NOP
> +	   instruction if no additional behavior beyond that of
> +	   SLLI is implemented.
> +
> +	   If you are not using the P8700 processor, say n.
> +
>   config ERRATA_SIFIVE
>   	bool "SiFive errata"
>   	depends on RISCV_ALTERNATIVE
> diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
> index bc6c77ba837d2da4c98dabab18083d27f46629c7..02a7a3335b1d557933e04cd6d0cf7bf4260b8c40 100644
> --- a/arch/riscv/errata/Makefile
> +++ b/arch/riscv/errata/Makefile
> @@ -13,5 +13,6 @@ endif
>   endif
>   
>   obj-$(CONFIG_ERRATA_ANDES) += andes/
> +obj-$(CONFIG_ERRATA_MIPS) += mips/
>   obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
>   obj-$(CONFIG_ERRATA_THEAD) += thead/
> diff --git a/arch/riscv/errata/mips/Makefile b/arch/riscv/errata/mips/Makefile
> new file mode 100644
> index 0000000000000000000000000000000000000000..6278c389b801ee6e54e808c80e6e236c026329c7
> --- /dev/null
> +++ b/arch/riscv/errata/mips/Makefile
> @@ -0,0 +1,5 @@
> +ifdef CONFIG_RISCV_ALTERNATIVE_EARLY
> +CFLAGS_errata.o := -mcmodel=medany
> +endif
> +
> +obj-y += errata.o
> diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errata.c
> new file mode 100644
> index 0000000000000000000000000000000000000000..e984a8152208c34690f89d8101571b097485c360
> --- /dev/null
> +++ b/arch/riscv/errata/mips/errata.c
> @@ -0,0 +1,67 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2025 MIPS.
> + */
> +
> +#include <linux/memory.h>
> +#include <linux/module.h>
> +#include <asm/text-patching.h>
> +#include <asm/alternative.h>
> +#include <asm/errata_list.h>
> +#include <asm/vendorid_list.h>
> +#include <asm/vendor_extensions.h>
> +#include <asm/vendor_extensions/mips.h>
> +
> +static inline bool errata_probe_pause(void)
> +{
> +	if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE))
> +		return false;
> +
> +	if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL))
> +		return false;
> +
> +	return true;
> +}
> +
> +static u32 mips_errata_probe(void)
> +{
> +	u32 cpu_req_errata = 0;
> +
> +	if (errata_probe_pause())
> +		cpu_req_errata |= BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE);
> +
> +	return cpu_req_errata;
> +}
> +
> +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> +			    unsigned long archid, unsigned long impid,
> +			    unsigned int stage)
> +{
> +	struct alt_entry *alt;
> +	u32 cpu_req_errata = mips_errata_probe();
> +	u32 tmp;
> +
> +	BUILD_BUG_ON(ERRATA_MIPS_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
> +
> +	if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
> +		return;
> +
> +	for (alt = begin; alt < end; alt++) {
> +		if (alt->vendor_id != MIPS_VENDOR_ID)
> +			continue;
> +
> +		if (alt->patch_id >= ERRATA_MIPS_NUMBER) {
> +			WARN(1, "MIPS errata id:%d not in kernel errata list\n",
> +			     alt->patch_id);
> +			continue;
> +		}
> +
> +		tmp = (1U << alt->patch_id);
> +		if (cpu_req_errata && tmp) {
> +			mutex_lock(&text_mutex);
> +			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
> +					  alt->alt_len);
> +			mutex_unlock(&text_mutex);
> +		}
> +	}
> +}
> diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
> index 3c2b59b25017929df92b4e6741ac1a9308bfec54..bc3ada8190a9e7dc7d904aeb3174c78329e4d8d7 100644
> --- a/arch/riscv/include/asm/alternative.h
> +++ b/arch/riscv/include/asm/alternative.h
> @@ -48,6 +48,9 @@ struct alt_entry {
>   void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>   			     unsigned long archid, unsigned long impid,
>   			     unsigned int stage);
> +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
> +			      unsigned long archid, unsigned long impid,
> +			      unsigned int stage);
>   void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>   			      unsigned long archid, unsigned long impid,
>   			      unsigned int stage);
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index 0b749e7102162477432f7cf9a34768fbdf2e8cc7..80bd52363c68690f33bfd54e0cc40399cd60b57b 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -14,6 +14,7 @@
>   #include <asm/insn-def.h>
>   #include <asm/cpufeature-macros.h>
>   #include <asm/processor.h>
> +#include <asm/errata_list.h>
>   
>   #define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append,		\
>   			   swap_append, r, p, n)				\
> @@ -438,7 +439,7 @@ static __always_inline void __cmpwait(volatile void *ptr,
>   	return;
>   
>   no_zawrs:
> -	asm volatile(RISCV_PAUSE : : : "memory");
> +	ALT_RISCV_PAUSE();
>   }
>   
>   #define __cmpwait_relaxed(ptr, val) \
> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
> index 6e426ed7919a4acd997b60b723c0d5cfddb4cff6..618dee38d8d1347711fd46a459bfc8d2cb7bf42b 100644
> --- a/arch/riscv/include/asm/errata_list.h
> +++ b/arch/riscv/include/asm/errata_list.h
> @@ -5,7 +5,6 @@
>   #ifndef ASM_ERRATA_LIST_H
>   #define ASM_ERRATA_LIST_H
>   
> -#include <asm/alternative.h>
>   #include <asm/csr.h>
>   #include <asm/insn-def.h>
>   #include <asm/hwcap.h>
> @@ -29,6 +28,11 @@
>   #define	ERRATA_THEAD_NUMBER 3
>   #endif
>   
> +#ifdef CONFIG_ERRATA_MIPS
> +#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0
> +#define ERRATA_MIPS_NUMBER 1
> +#endif
> +
>   #ifdef __ASSEMBLY__
>   
>   #define ALT_INSN_FAULT(x)						\
> @@ -59,6 +63,17 @@ asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID,	\
>   		ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)	\
>   		: : "r" (addr), "r" (asid) : "memory")
>   
> +#define ALT_RISCV_PAUSE()					\
> +asm(ALTERNATIVE(	\
> +		RISCV_PAUSE, /* Original RISC‑V pause insn */	\
> +		".4byte 0x00501013", /* Replacement for MIPS P8700 */	\


Here  you should use MIPS_PAUSE


> +		MIPS_VENDOR_ID, /* Vendor ID to match */	\
> +		ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */	\
> +		CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)	\
> +	: /* no outputs */	\
> +	: /* no inputs */	\
> +	: "memory")
> +
>   /*
>    * _val is marked as "will be overwritten", so need to set it to 0
>    * in the default case.
> diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
> index 8f383f05a290f123d941226b5dd975381d7d8536..8f749552ecfe6220bbc35f1c4677c6de8f7abdec 100644
> --- a/arch/riscv/include/asm/vdso/processor.h
> +++ b/arch/riscv/include/asm/vdso/processor.h
> @@ -5,6 +5,8 @@
>   #ifndef __ASSEMBLY__
>   
>   #include <asm/barrier.h>
> +


New line ^


> +#include <asm/errata_list.h>
>   #include <asm/insn-def.h>
>   
>   static inline void cpu_relax(void)
> @@ -19,7 +21,7 @@ static inline void cpu_relax(void)
>   	 * Reduce instruction retirement.
>   	 * This assumes the PC changes.
>   	 */
> -	__asm__ __volatile__ (RISCV_PAUSE);
> +	ALT_RISCV_PAUSE();
>   	barrier();
>   }
>   
> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
> index a5150cdf34d87f01baf6d3ef843bc2d6d8d54095..3b09874d7a6dfb8f8aa45b0be41c20711d539e78 100644
> --- a/arch/riscv/include/asm/vendorid_list.h
> +++ b/arch/riscv/include/asm/vendorid_list.h
> @@ -9,5 +9,6 @@
>   #define MICROCHIP_VENDOR_ID	0x029
>   #define SIFIVE_VENDOR_ID	0x489
>   #define THEAD_VENDOR_ID		0x5b7
> +#define MIPS_VENDOR_ID		0x722
>   
>   #endif
> diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
> index 7eb3cb1215c62130c63a72fc650cddff6bae62af..7642704c7f1841f67fc23738063f22b4ecf58194 100644
> --- a/arch/riscv/kernel/alternative.c
> +++ b/arch/riscv/kernel/alternative.c
> @@ -47,6 +47,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
>   		cpu_mfr_info->patch_func = andes_errata_patch_func;
>   		break;
>   #endif
> +#ifdef CONFIG_ERRATA_MIPS
> +	case MIPS_VENDOR_ID:
> +		cpu_mfr_info->patch_func = mips_errata_patch_func;
> +		break;
> +#endif
>   #ifdef CONFIG_ERRATA_SIFIVE
>   	case SIFIVE_VENDOR_ID:
>   		cpu_mfr_info->patch_func = sifive_errata_patch_func;
> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> index 75656afa2d6be8ca5f2c4711455567c7f8fc0b97..b18373ed23d65df0dc828246269e9039bb0b0c6b 100644
> --- a/arch/riscv/kernel/entry.S
> +++ b/arch/riscv/kernel/entry.S
> @@ -15,6 +15,8 @@
>   #include <asm/thread_info.h>
>   #include <asm/asm-offsets.h>
>   #include <asm/errata_list.h>
> +#include <asm/alternative.h>
> +
>   #include <linux/sizes.h>
>   
>   	.section .irqentry.text, "ax"
> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
> index 8d0374d7ce8ed72320f58e4cea212d0e2bce8fd4..7ee95ebadc258a3a46e59698cd143266f6797a0c 100644
> --- a/arch/riscv/mm/init.c
> +++ b/arch/riscv/mm/init.c
> @@ -33,6 +33,7 @@
>   #include <asm/soc.h>
>   #include <asm/sparsemem.h>
>   #include <asm/tlbflush.h>
> +#include <asm/alternative.h>
>   
>   #include "../kernel/head.h"
>   
>
Why do you include alternative.h in both files above? That does not seem 
needed.

Other than that:

Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>

Thanks,

Alex

Re: [PATCH v4 0/7] riscv: Add support for xmipsexectl

[Alexandre Ghiti]

On 6/25/25 16:20, Aleksa Paunovic via B4 Relay wrote:
> This patch series adds support for the xmipsexectl vendor extension.
> A new hardware probe key has also been added to allow userspace to probe for MIPS vendor extensions.
>
> Additionally, since the standard Zihintpause PAUSE instruction encoding is not supported on some MIPS CPUs,
> an errata was implemented for replacing this instruction with the xmipsexectl MIPS.PAUSE alternative encoding.
>
> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
> ---
> This is a continuation of a previous series, which did not implement the full
> xmipsexectl vendor extension. The title was updated accordingly.
>
> Changes in v4:
> - Add support for the xmipsexectl vendor extension
> - Remove the ifdef/else from errata_list.h
> - Replace the ifdef/else with a hwprobe call in the userspace code.
>
> Link to v3:
> https://lore.kernel.org/linux-riscv/20250129131703.733098-1-arikalo@gmail.com/
>
> ---
> Aleksa Paunovic (6):
>        dt-bindings: riscv: Add xmipsexectl ISA extension description
>        riscv: Add xmipsexectl as a vendor extension
>        riscv: Add xmipsexectl PAUSE instruction
>        riscv: hwprobe: Add MIPS vendor extension probing
>        riscv: hwprobe: Document MIPS xmipsexectl vendor extension
>        riscv: Add tools support for xmipsexectl
>
> Djordje Todorovic (1):
>        riscv: errata: Fix the PAUSE Opcode for MIPS P8700
>
>   Documentation/arch/riscv/hwprobe.rst               |  9 +++
>   .../devicetree/bindings/riscv/extensions.yaml      |  6 ++
>   arch/riscv/Kconfig.errata                          | 23 ++++++++
>   arch/riscv/Kconfig.vendor                          | 13 +++++
>   arch/riscv/errata/Makefile                         |  1 +
>   arch/riscv/errata/mips/Makefile                    |  5 ++
>   arch/riscv/errata/mips/errata.c                    | 67 ++++++++++++++++++++++
>   arch/riscv/include/asm/alternative.h               |  3 +
>   arch/riscv/include/asm/cmpxchg.h                   |  3 +-
>   arch/riscv/include/asm/errata_list.h               | 17 +++++-
>   arch/riscv/include/asm/hwprobe.h                   |  3 +-
>   arch/riscv/include/asm/vdso/processor.h            |  4 +-
>   arch/riscv/include/asm/vendor_extensions/mips.h    | 23 ++++++++
>   .../include/asm/vendor_extensions/mips_hwprobe.h   | 23 ++++++++
>   arch/riscv/include/asm/vendorid_list.h             |  1 +
>   arch/riscv/include/uapi/asm/hwprobe.h              |  1 +
>   arch/riscv/include/uapi/asm/vendor/mips.h          |  3 +
>   arch/riscv/kernel/alternative.c                    |  5 ++
>   arch/riscv/kernel/entry.S                          |  2 +
>   arch/riscv/kernel/sys_hwprobe.c                    |  4 ++
>   arch/riscv/kernel/vendor_extensions.c              | 10 ++++
>   arch/riscv/kernel/vendor_extensions/Makefile       |  2 +
>   arch/riscv/kernel/vendor_extensions/mips.c         | 22 +++++++
>   arch/riscv/kernel/vendor_extensions/mips_hwprobe.c | 22 +++++++
>   arch/riscv/mm/init.c                               |  1 +
>   tools/arch/riscv/include/asm/vdso/processor.h      | 27 +++++----
>   26 files changed, 286 insertions(+), 14 deletions(-)
> ---
> base-commit: 19272b37aa4f83ca52bdf9c16d5d81bdd1354494
> change-id: 20250424-p8700-pause-dcb649968e24
>
> Best regards,


I tried to fix all the small comments I added, but there are quite a few 
(and using MIPS_PAUSE triggered a new header nightmare) so can you send 
another version rebased on top of this branch 
https://git.kernel.org/pub/scm/linux/kernel/git/alexghiti/linux.git/log/?h=alex-for-next 
?

Thanks,

Alex

Re: [PATCH v4 7/7] riscv: errata: Fix the PAUSE Opcode for MIPS P8700

[Aleksa Paunovic]

On 17. 7. 25. 13:43, Alexandre Ghiti wrote:
> On 6/25/25 16:21, Aleksa Paunovic via B4 Relay wrote:
>> From: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>>
>> Add ERRATA_MIPS and ERRATA_MIPS_P8700_PAUSE_OPCODE configs.
>> Handle errata for the MIPS PAUSE instruction.
>>
>> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
>> Signed-off-by: Aleksandar Rikalo <arikalo@gmail.com>
>> Signed-off-by: Raj Vishwanathan4 <rvishwanathan@mips.com>
>> Signed-off-by: Aleksa Paunovic <aleksa.paunovic@htecgroup.com>
>> ---
>>   arch/riscv/Kconfig.errata               | 23 +++++++++++
>>   arch/riscv/errata/Makefile              |  1 +
>>   arch/riscv/errata/mips/Makefile         |  5 +++
>>   arch/riscv/errata/mips/errata.c         | 67 +++++++++++++++++++++++++++++++++
>>   arch/riscv/include/asm/alternative.h    |  3 ++
>>   arch/riscv/include/asm/cmpxchg.h        |  3 +-
>>   arch/riscv/include/asm/errata_list.h    | 17 ++++++++-
>>   arch/riscv/include/asm/vdso/processor.h |  4 +-
>>   arch/riscv/include/asm/vendorid_list.h  |  1 +
>>   arch/riscv/kernel/alternative.c         |  5 +++
>>   arch/riscv/kernel/entry.S               |  2 +
>>   arch/riscv/mm/init.c                    |  1 +
>>   12 files changed, 129 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
>> index e318119d570de0acc0850a2e1a2505ecb71bea08..aca9b0cfcfecf91d4d1910f294ee109ed15f2d6c 100644
>> --- a/arch/riscv/Kconfig.errata
>> +++ b/arch/riscv/Kconfig.errata
>> @@ -21,6 +21,29 @@ config ERRATA_ANDES_CMO
>>
>>         If you don't know what to do here, say "Y".
>>
>> +config ERRATA_MIPS
>> +     bool "MIPS errata"
>> +     depends on RISCV_ALTERNATIVE
>> +     help
>> +       All MIPS errata Kconfig depend on this Kconfig. Disabling
>> +       this Kconfig will disable all MIPS errata. Please say "Y"
>> +       here if your platform uses MIPS CPU cores.
>> +
>> +       Otherwise, please say "N" here to avoid unnecessary overhead.
>> +
>> +config ERRATA_MIPS_P8700_PAUSE_OPCODE
>> +     bool "Fix the PAUSE Opcode for MIPS P8700"
>> +     depends on ERRATA_MIPS && 64BIT
>> +     default n
>> +     help
>> +        The RISCV MIPS P8700 uses a different opcode for PAUSE.
>> +        It is a 'hint' encoding of the SLLI instruction,
>> +        with rd=0, rs1=0 and imm=5. It will behave as a NOP
>> +        instruction if no additional behavior beyond that of
>> +        SLLI is implemented.
>> +
>> +        If you are not using the P8700 processor, say n.
>> +
>>   config ERRATA_SIFIVE
>>       bool "SiFive errata"
>>       depends on RISCV_ALTERNATIVE
>> diff --git a/arch/riscv/errata/Makefile b/arch/riscv/errata/Makefile
>> index bc6c77ba837d2da4c98dabab18083d27f46629c7..02a7a3335b1d557933e04cd6d0cf7bf4260b8c40 100644
>> --- a/arch/riscv/errata/Makefile
>> +++ b/arch/riscv/errata/Makefile
>> @@ -13,5 +13,6 @@ endif
>>   endif
>>
>>   obj-$(CONFIG_ERRATA_ANDES) += andes/
>> +obj-$(CONFIG_ERRATA_MIPS) += mips/
>>   obj-$(CONFIG_ERRATA_SIFIVE) += sifive/
>>   obj-$(CONFIG_ERRATA_THEAD) += thead/
>> diff --git a/arch/riscv/errata/mips/Makefile b/arch/riscv/errata/mips/Makefile
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..6278c389b801ee6e54e808c80e6e236c026329c7
>> --- /dev/null
>> +++ b/arch/riscv/errata/mips/Makefile
>> @@ -0,0 +1,5 @@
>> +ifdef CONFIG_RISCV_ALTERNATIVE_EARLY
>> +CFLAGS_errata.o := -mcmodel=medany
>> +endif
>> +
>> +obj-y += errata.o
>> diff --git a/arch/riscv/errata/mips/errata.c b/arch/riscv/errata/mips/errata.c
>> new file mode 100644
>> index 0000000000000000000000000000000000000000..e984a8152208c34690f89d8101571b097485c360
>> --- /dev/null
>> +++ b/arch/riscv/errata/mips/errata.c
>> @@ -0,0 +1,67 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (C) 2025 MIPS.
>> + */
>> +
>> +#include <linux/memory.h>
>> +#include <linux/module.h>
>> +#include <asm/text-patching.h>
>> +#include <asm/alternative.h>
>> +#include <asm/errata_list.h>
>> +#include <asm/vendorid_list.h>
>> +#include <asm/vendor_extensions.h>
>> +#include <asm/vendor_extensions/mips.h>
>> +
>> +static inline bool errata_probe_pause(void)
>> +{
>> +     if (!IS_ENABLED(CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE))
>> +             return false;
>> +
>> +     if (!riscv_isa_vendor_extension_available(MIPS_VENDOR_ID, XMIPSEXECTL))
>> +             return false;
>> +
>> +     return true;
>> +}
>> +
>> +static u32 mips_errata_probe(void)
>> +{
>> +     u32 cpu_req_errata = 0;
>> +
>> +     if (errata_probe_pause())
>> +             cpu_req_errata |= BIT(ERRATA_MIPS_P8700_PAUSE_OPCODE);
>> +
>> +     return cpu_req_errata;
>> +}
>> +
>> +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>> +                         unsigned long archid, unsigned long impid,
>> +                         unsigned int stage)
>> +{
>> +     struct alt_entry *alt;
>> +     u32 cpu_req_errata = mips_errata_probe();
>> +     u32 tmp;
>> +
>> +     BUILD_BUG_ON(ERRATA_MIPS_NUMBER >= RISCV_VENDOR_EXT_ALTERNATIVES_BASE);
>> +
>> +     if (stage == RISCV_ALTERNATIVES_EARLY_BOOT)
>> +             return;
>> +
>> +     for (alt = begin; alt < end; alt++) {
>> +             if (alt->vendor_id != MIPS_VENDOR_ID)
>> +                     continue;
>> +
>> +             if (alt->patch_id >= ERRATA_MIPS_NUMBER) {
>> +                     WARN(1, "MIPS errata id:%d not in kernel errata list\n",
>> +                          alt->patch_id);
>> +                     continue;
>> +             }
>> +
>> +             tmp = (1U << alt->patch_id);
>> +             if (cpu_req_errata && tmp) {
>> +                     mutex_lock(&text_mutex);
>> +                     patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),
>> +                                       alt->alt_len);
>> +                     mutex_unlock(&text_mutex);
>> +             }
>> +     }
>> +}
>> diff --git a/arch/riscv/include/asm/alternative.h b/arch/riscv/include/asm/alternative.h
>> index 3c2b59b25017929df92b4e6741ac1a9308bfec54..bc3ada8190a9e7dc7d904aeb3174c78329e4d8d7 100644
>> --- a/arch/riscv/include/asm/alternative.h
>> +++ b/arch/riscv/include/asm/alternative.h
>> @@ -48,6 +48,9 @@ struct alt_entry {
>>   void andes_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>>                            unsigned long archid, unsigned long impid,
>>                            unsigned int stage);
>> +void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>> +                           unsigned long archid, unsigned long impid,
>> +                           unsigned int stage);
>>   void sifive_errata_patch_func(struct alt_entry *begin, struct alt_entry *end,
>>                             unsigned long archid, unsigned long impid,
>>                             unsigned int stage);
>> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
>> index 0b749e7102162477432f7cf9a34768fbdf2e8cc7..80bd52363c68690f33bfd54e0cc40399cd60b57b 100644
>> --- a/arch/riscv/include/asm/cmpxchg.h
>> +++ b/arch/riscv/include/asm/cmpxchg.h
>> @@ -14,6 +14,7 @@
>>   #include <asm/insn-def.h>
>>   #include <asm/cpufeature-macros.h>
>>   #include <asm/processor.h>
>> +#include <asm/errata_list.h>
>>
>>   #define __arch_xchg_masked(sc_sfx, swap_sfx, prepend, sc_append,            \
>>                          swap_append, r, p, n)                                \
>> @@ -438,7 +439,7 @@ static __always_inline void __cmpwait(volatile void *ptr,
>>       return;
>>
>>   no_zawrs:
>> -     asm volatile(RISCV_PAUSE : : : "memory");
>> +     ALT_RISCV_PAUSE();
>>   }
>>
>>   #define __cmpwait_relaxed(ptr, val) \
>> diff --git a/arch/riscv/include/asm/errata_list.h b/arch/riscv/include/asm/errata_list.h
>> index 6e426ed7919a4acd997b60b723c0d5cfddb4cff6..618dee38d8d1347711fd46a459bfc8d2cb7bf42b 100644
>> --- a/arch/riscv/include/asm/errata_list.h
>> +++ b/arch/riscv/include/asm/errata_list.h
>> @@ -5,7 +5,6 @@
>>   #ifndef ASM_ERRATA_LIST_H
>>   #define ASM_ERRATA_LIST_H
>>
>> -#include <asm/alternative.h>
>>   #include <asm/csr.h>
>>   #include <asm/insn-def.h>
>>   #include <asm/hwcap.h>
>> @@ -29,6 +28,11 @@
>>   #define     ERRATA_THEAD_NUMBER 3
>>   #endif
>>
>> +#ifdef CONFIG_ERRATA_MIPS
>> +#define ERRATA_MIPS_P8700_PAUSE_OPCODE 0
>> +#define ERRATA_MIPS_NUMBER 1
>> +#endif
>> +
>>   #ifdef __ASSEMBLY__
>>
>>   #define ALT_INSN_FAULT(x)                                           \
>> @@ -59,6 +63,17 @@ asm(ALTERNATIVE("sfence.vma %0, %1", "sfence.vma", SIFIVE_VENDOR_ID,       \
>>               ERRATA_SIFIVE_CIP_1200, CONFIG_ERRATA_SIFIVE_CIP_1200)  \
>>               : : "r" (addr), "r" (asid) : "memory")
>>
>> +#define ALT_RISCV_PAUSE()                                    \
>> +asm(ALTERNATIVE(     \
>> +             RISCV_PAUSE, /* Original RISC‑V pause insn */   \
>> +             ".4byte 0x00501013", /* Replacement for MIPS P8700 */   \
> 
> 
> Here  you should use MIPS_PAUSE
> 
> 
>> +             MIPS_VENDOR_ID, /* Vendor ID to match */        \
>> +             ERRATA_MIPS_P8700_PAUSE_OPCODE, /* patch_id */  \
>> +             CONFIG_ERRATA_MIPS_P8700_PAUSE_OPCODE)  \
>> +     : /* no outputs */      \
>> +     : /* no inputs */       \
>> +     : "memory")
>> +
>>   /*
>>    * _val is marked as "will be overwritten", so need to set it to 0
>>    * in the default case.
>> diff --git a/arch/riscv/include/asm/vdso/processor.h b/arch/riscv/include/asm/vdso/processor.h
>> index 8f383f05a290f123d941226b5dd975381d7d8536..8f749552ecfe6220bbc35f1c4677c6de8f7abdec 100644
>> --- a/arch/riscv/include/asm/vdso/processor.h
>> +++ b/arch/riscv/include/asm/vdso/processor.h
>> @@ -5,6 +5,8 @@
>>   #ifndef __ASSEMBLY__
>>
>>   #include <asm/barrier.h>
>> +
> 
> 
> New line ^
> 
> 
>> +#include <asm/errata_list.h>
>>   #include <asm/insn-def.h>
>>
>>   static inline void cpu_relax(void)
>> @@ -19,7 +21,7 @@ static inline void cpu_relax(void)
>>        * Reduce instruction retirement.
>>        * This assumes the PC changes.
>>        */
>> -     __asm__ __volatile__ (RISCV_PAUSE);
>> +     ALT_RISCV_PAUSE();
>>       barrier();
>>   }
>>
>> diff --git a/arch/riscv/include/asm/vendorid_list.h b/arch/riscv/include/asm/vendorid_list.h
>> index a5150cdf34d87f01baf6d3ef843bc2d6d8d54095..3b09874d7a6dfb8f8aa45b0be41c20711d539e78 100644
>> --- a/arch/riscv/include/asm/vendorid_list.h
>> +++ b/arch/riscv/include/asm/vendorid_list.h
>> @@ -9,5 +9,6 @@
>>   #define MICROCHIP_VENDOR_ID 0x029
>>   #define SIFIVE_VENDOR_ID    0x489
>>   #define THEAD_VENDOR_ID             0x5b7
>> +#define MIPS_VENDOR_ID               0x722
>>
>>   #endif
>> diff --git a/arch/riscv/kernel/alternative.c b/arch/riscv/kernel/alternative.c
>> index 7eb3cb1215c62130c63a72fc650cddff6bae62af..7642704c7f1841f67fc23738063f22b4ecf58194 100644
>> --- a/arch/riscv/kernel/alternative.c
>> +++ b/arch/riscv/kernel/alternative.c
>> @@ -47,6 +47,11 @@ static void riscv_fill_cpu_mfr_info(struct cpu_manufacturer_info_t *cpu_mfr_info
>>               cpu_mfr_info->patch_func = andes_errata_patch_func;
>>               break;
>>   #endif
>> +#ifdef CONFIG_ERRATA_MIPS
>> +     case MIPS_VENDOR_ID:
>> +             cpu_mfr_info->patch_func = mips_errata_patch_func;
>> +             break;
>> +#endif
>>   #ifdef CONFIG_ERRATA_SIFIVE
>>       case SIFIVE_VENDOR_ID:
>>               cpu_mfr_info->patch_func = sifive_errata_patch_func;
>> diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
>> index 75656afa2d6be8ca5f2c4711455567c7f8fc0b97..b18373ed23d65df0dc828246269e9039bb0b0c6b 100644
>> --- a/arch/riscv/kernel/entry.S
>> +++ b/arch/riscv/kernel/entry.S
>> @@ -15,6 +15,8 @@
>>   #include <asm/thread_info.h>
>>   #include <asm/asm-offsets.h>
>>   #include <asm/errata_list.h>
>> +#include <asm/alternative.h>
>> +
>>   #include <linux/sizes.h>
>>
>>       .section .irqentry.text, "ax"
>> diff --git a/arch/riscv/mm/init.c b/arch/riscv/mm/init.c
>> index 8d0374d7ce8ed72320f58e4cea212d0e2bce8fd4..7ee95ebadc258a3a46e59698cd143266f6797a0c 100644
>> --- a/arch/riscv/mm/init.c
>> +++ b/arch/riscv/mm/init.c
>> @@ -33,6 +33,7 @@
>>   #include <asm/soc.h>
>>   #include <asm/sparsemem.h>
>>   #include <asm/tlbflush.h>
>> +#include <asm/alternative.h>
>>
>>   #include "../kernel/head.h"
>>
>>
> Why do you include alternative.h in both files above? That does not seem
> needed. 
Hi Alexandre,

Thank you for reviewing the series.

We ran into similar header problems with these as we did with mips.h. Moving alternative.h 
from errata_list.h to init.c seemed like the simplest solution. Including into 
entry.S does seem unnecessary, though.

I addressed the rest of your comments in v5.

Best regards,
Aleksa

> 
> Other than that:
> 
> Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> 
> Thanks,
> 
> Alex