From: Baolu Lu <baolu.lu@linux.intel.com>
To: "Tian, Kevin" <kevin.tian@intel.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Jason Gunthorpe <jgg@ziepe.ca>
Cc: baolu.lu@linux.intel.com,
"iommu@lists.linux.dev" <iommu@lists.linux.dev>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v3 1/2] iommu/vt-d: Add helper to flush caches for context change
Date: Tue, 2 Jul 2024 12:51:12 +0800 [thread overview]
Message-ID: <1c9204d9-d9da-4785-b375-368b5ba9ec78@linux.intel.com> (raw)
In-Reply-To: <5a8802e3-feda-49bf-b11b-2ba6c236305e@linux.intel.com>
On 2024/7/2 10:43, Baolu Lu wrote:
> On 7/2/24 9:47 AM, Baolu Lu wrote:
>> On 7/2/24 9:11 AM, Tian, Kevin wrote:
>>>> From: Lu Baolu<baolu.lu@linux.intel.com>
>>>> Sent: Monday, July 1, 2024 7:23 PM
>>>> +
>>>> + /*
>>>> + * For scalable mode:
>>>> + * - Domain-selective PASID-cache invalidation to affected domains
>>>> + * - Domain-selective IOTLB invalidation to affected domains
>>>> + * - Global Device-TLB invalidation to affected functions
>>>> + */
>>>> + if (flush_domains) {
>>>> + /*
>>>> + * If the IOMMU is running in scalable mode and there might
>>>> + * be potential PASID translations, the caller should hold
>>>> + * the lock to ensure that context changes and cache flushes
>>>> + * are atomic.
>>>> + */
>>>> + assert_spin_locked(&iommu->lock);
>>>> + for (i = 0; i < info->pasid_table->max_pasid; i++) {
>>>> + pte = intel_pasid_get_entry(info->dev, i);
>>>> + if (!pte || !pasid_pte_is_present(pte))
>>>> + continue;
>>>> +
>>>> + did = pasid_get_domain_id(pte);
>>>> + qi_flush_pasid_cache(iommu, did,
>>>> QI_PC_ALL_PASIDS, 0);
>>>> + iommu->flush.flush_iotlb(iommu, did, 0, 0,
>>>> DMA_TLB_DSI_FLUSH);
>>>> + }
>>>> + }
>>>> +
>>>> + __context_flush_dev_iotlb(info);
>>>> +}
>>> this only invalidates devtlb w/o PASID. We miss a pasid devtlb
>>> invalidation
>>> with global bit set.
>>
>> I am not sure about this. The spec says "Global Device-TLB invalidation
>> to affected functions", I am not sure whether this implies any PASID-
>> based-Device-TLB invalidation.
>
> I just revisited the spec, Device-TLB invalidation only covers caches
> for requests-without-PASID. If pasid translation is affected while
> updating the context entry, we should also take care of the caches for
> requests-with-pasid.
>
> I will add below line to address this.
>
> diff --git a/drivers/iommu/intel/pasid.c b/drivers/iommu/intel/pasid.c
> index 9a7b5668c723..91db0876682e 100644
> --- a/drivers/iommu/intel/pasid.c
> +++ b/drivers/iommu/intel/pasid.c
> @@ -932,6 +932,7 @@ void intel_context_flush_present(struct
> device_domain_info *info,
> did = pasid_get_domain_id(pte);
> qi_flush_pasid_cache(iommu, did,
> QI_PC_ALL_PASIDS, 0);
> iommu->flush.flush_iotlb(iommu, did, 0, 0,
> DMA_TLB_DSI_FLUSH);
> + pasid_cache_invalidation_with_pasid(iommu, did, i);
Should be
devtlb_invalidation_with_pasid(iommu, info->dev, i);
Sorry for the typo.
Best regards,
baolu
next prev parent reply other threads:[~2024-07-02 4:51 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-07-01 11:23 [PATCH v3 0/2] iommu/vt-d: Refactor PRI enable/disable steps Lu Baolu
2024-07-01 11:23 ` [PATCH v3 1/2] iommu/vt-d: Add helper to flush caches for context change Lu Baolu
2024-07-02 1:11 ` Tian, Kevin
2024-07-02 1:47 ` Baolu Lu
2024-07-02 2:43 ` Baolu Lu
2024-07-02 4:51 ` Baolu Lu [this message]
2024-07-02 6:25 ` Yi Liu
2024-07-02 6:39 ` Tian, Kevin
2024-07-02 8:03 ` Baolu Lu
2024-07-02 4:41 ` Jacob Pan
2024-07-02 4:43 ` Baolu Lu
2024-07-02 15:57 ` Jacob Pan
2024-07-03 2:49 ` Baolu Lu
2024-07-03 21:35 ` Jacob Pan
2024-07-01 11:23 ` [PATCH v3 2/2] iommu/vt-d: Refactor PCI PRI enabling/disabling callbacks Lu Baolu
2024-07-02 1:11 ` Tian, Kevin
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