From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A59DF12D1F1 for ; Fri, 8 Nov 2024 20:32:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.12 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731097923; cv=none; b=ZZW5Vfk3DxOYe/BDvest53OBzamb0mnY6XyIMlqcQGJin7Y31GOnTq182iAgQSTX1oqjyvd7E6dJ6LiFpiYw/jW7ha7ACfocuRBXd3G1TbmvX9DU1EPu6Sxa2irJuSEi0KsYvpJsuBT/0qibqB7iARn/3/Ri1//qTP0CZt55g7A= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1731097923; c=relaxed/simple; bh=NKBk2ZaWykfkWFx9/6PZcHPKXs8zb1gW7eKm9SIOxsM=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=ehdunbYBY6glO7FlNYN/E/LbsKX56zabVA3kc17mcSToKbYbIwppt/BQO1kDhqI+DCNeYHNJFA7KF4fT5/ihjHi+Kk2OccRwbQi6uTBASNHHvu4MGBO1MjXGu4ec85X1hbU87rk5aDFxO1gngeBmV98uD7UTPMePn6Pe2owEO7o= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Wpz5B7or; arc=none smtp.client-ip=192.198.163.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Wpz5B7or" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1731097921; x=1762633921; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=NKBk2ZaWykfkWFx9/6PZcHPKXs8zb1gW7eKm9SIOxsM=; b=Wpz5B7or17g55sDZtlbtyVDkaFYZDECozALUPFGx1lKZqN7IwrzPKCh5 PW/ZiuTgxiXifL+f0iiOpUrEkuOIrCKEKKi1Kz6JtVRQ73Fiibg9wMoqM SHiKXaMaxxkPiFl1OjLR28vtC1QYxsOVCmtN6knt4J60XZ8iE9VrYH6wy 9ADLpciWP7PVdUTA+6cYWh1BrLyyAs9YmCBk0kq3uizo5sOxtZKGUw5ZE ThaLFIIfZ2hIGiKvKS0Z+1kzba/Rc5iWz9qppONqFZtWX0LV4aPo3QjHW NOj8SJepucrMmiiV+ceNQg2yDvgnOCE/Zo21b2S+EsC9bOZssrcgWRKVr A==; X-CSE-ConnectionGUID: DlF2wbllSt+QIdtKTO77kw== X-CSE-MsgGUID: iezjNXFiRx+Ku+1M3phfFw== X-IronPort-AV: E=McAfee;i="6700,10204,11250"; a="34932523" X-IronPort-AV: E=Sophos;i="6.12,138,1728975600"; d="scan'208";a="34932523" Received: from fmviesa005.fm.intel.com ([10.60.135.145]) by fmvoesa106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2024 12:31:57 -0800 X-CSE-ConnectionGUID: YA4/rwkET0unXZJ8HJeWFg== X-CSE-MsgGUID: soKTt85USniXdvuVSjLIOw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,138,1728975600"; d="scan'208";a="90257044" Received: from rfrazer-mobl3.amr.corp.intel.com (HELO [10.124.223.66]) ([10.124.223.66]) by fmviesa005-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 08 Nov 2024 12:31:57 -0800 Message-ID: <1df2caa3-4c5d-4bd9-88bb-66a07bf1eb65@intel.com> Date: Fri, 8 Nov 2024 12:31:56 -0800 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] x86,tlb: update mm_cpumask lazily To: Rik van Riel , Dave Hansen Cc: Andy Lutomirski , Peter Zijlstra , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H. Peter Anvin" , linux-kernel@vger.kernel.org, kernel-team@meta.com References: <20241108143144.2f15fe35@imladris.surriel.com> From: Dave Hansen Content-Language: en-US Autocrypt: addr=dave.hansen@intel.com; keydata= xsFNBE6HMP0BEADIMA3XYkQfF3dwHlj58Yjsc4E5y5G67cfbt8dvaUq2fx1lR0K9h1bOI6fC oAiUXvGAOxPDsB/P6UEOISPpLl5IuYsSwAeZGkdQ5g6m1xq7AlDJQZddhr/1DC/nMVa/2BoY 2UnKuZuSBu7lgOE193+7Uks3416N2hTkyKUSNkduyoZ9F5twiBhxPJwPtn/wnch6n5RsoXsb ygOEDxLEsSk/7eyFycjE+btUtAWZtx+HseyaGfqkZK0Z9bT1lsaHecmB203xShwCPT49Blxz VOab8668QpaEOdLGhtvrVYVK7x4skyT3nGWcgDCl5/Vp3TWA4K+IofwvXzX2ON/Mj7aQwf5W iC+3nWC7q0uxKwwsddJ0Nu+dpA/UORQWa1NiAftEoSpk5+nUUi0WE+5DRm0H+TXKBWMGNCFn c6+EKg5zQaa8KqymHcOrSXNPmzJuXvDQ8uj2J8XuzCZfK4uy1+YdIr0yyEMI7mdh4KX50LO1 pmowEqDh7dLShTOif/7UtQYrzYq9cPnjU2ZW4qd5Qz2joSGTG9eCXLz5PRe5SqHxv6ljk8mb ApNuY7bOXO/A7T2j5RwXIlcmssqIjBcxsRRoIbpCwWWGjkYjzYCjgsNFL6rt4OL11OUF37wL QcTl7fbCGv53KfKPdYD5hcbguLKi/aCccJK18ZwNjFhqr4MliQARAQABzUVEYXZpZCBDaHJp c3RvcGhlciBIYW5zZW4gKEludGVsIFdvcmsgQWRkcmVzcykgPGRhdmUuaGFuc2VuQGludGVs LmNvbT7CwXgEEwECACIFAlQ+9J0CGwMGCwkIBwMCBhUIAgkKCwQWAgMBAh4BAheAAAoJEGg1 lTBwyZKwLZUP/0dnbhDc229u2u6WtK1s1cSd9WsflGXGagkR6liJ4um3XCfYWDHvIdkHYC1t MNcVHFBwmQkawxsYvgO8kXT3SaFZe4ISfB4K4CL2qp4JO+nJdlFUbZI7cz/Td9z8nHjMcWYF IQuTsWOLs/LBMTs+ANumibtw6UkiGVD3dfHJAOPNApjVr+M0P/lVmTeP8w0uVcd2syiaU5jB aht9CYATn+ytFGWZnBEEQFnqcibIaOrmoBLu2b3fKJEd8Jp7NHDSIdrvrMjYynmc6sZKUqH2 I1qOevaa8jUg7wlLJAWGfIqnu85kkqrVOkbNbk4TPub7VOqA6qG5GCNEIv6ZY7HLYd/vAkVY E8Plzq/NwLAuOWxvGrOl7OPuwVeR4hBDfcrNb990MFPpjGgACzAZyjdmYoMu8j3/MAEW4P0z F5+EYJAOZ+z212y1pchNNauehORXgjrNKsZwxwKpPY9qb84E3O9KYpwfATsqOoQ6tTgr+1BR CCwP712H+E9U5HJ0iibN/CDZFVPL1bRerHziuwuQuvE0qWg0+0SChFe9oq0KAwEkVs6ZDMB2 P16MieEEQ6StQRlvy2YBv80L1TMl3T90Bo1UUn6ARXEpcbFE0/aORH/jEXcRteb+vuik5UGY 5TsyLYdPur3TXm7XDBdmmyQVJjnJKYK9AQxj95KlXLVO38lczsFNBFRjzmoBEACyAxbvUEhd GDGNg0JhDdezyTdN8C9BFsdxyTLnSH31NRiyp1QtuxvcqGZjb2trDVuCbIzRrgMZLVgo3upr MIOx1CXEgmn23Zhh0EpdVHM8IKx9Z7V0r+rrpRWFE8/wQZngKYVi49PGoZj50ZEifEJ5qn/H Nsp2+Y+bTUjDdgWMATg9DiFMyv8fvoqgNsNyrrZTnSgoLzdxr89FGHZCoSoAK8gfgFHuO54B lI8QOfPDG9WDPJ66HCodjTlBEr/Cwq6GruxS5i2Y33YVqxvFvDa1tUtl+iJ2SWKS9kCai2DR 3BwVONJEYSDQaven/EHMlY1q8Vln3lGPsS11vSUK3QcNJjmrgYxH5KsVsf6PNRj9mp8Z1kIG qjRx08+nnyStWC0gZH6NrYyS9rpqH3j+hA2WcI7De51L4Rv9pFwzp161mvtc6eC/GxaiUGuH BNAVP0PY0fqvIC68p3rLIAW3f97uv4ce2RSQ7LbsPsimOeCo/5vgS6YQsj83E+AipPr09Caj 0hloj+hFoqiticNpmsxdWKoOsV0PftcQvBCCYuhKbZV9s5hjt9qn8CE86A5g5KqDf83Fxqm/ vXKgHNFHE5zgXGZnrmaf6resQzbvJHO0Fb0CcIohzrpPaL3YepcLDoCCgElGMGQjdCcSQ+Ci FCRl0Bvyj1YZUql+ZkptgGjikQARAQABwsFfBBgBAgAJBQJUY85qAhsMAAoJEGg1lTBwyZKw l4IQAIKHs/9po4spZDFyfDjunimEhVHqlUt7ggR1Hsl/tkvTSze8pI1P6dGp2XW6AnH1iayn yRcoyT0ZJ+Zmm4xAH1zqKjWplzqdb/dO28qk0bPso8+1oPO8oDhLm1+tY+cOvufXkBTm+whm +AyNTjaCRt6aSMnA/QHVGSJ8grrTJCoACVNhnXg/R0g90g8iV8Q+IBZyDkG0tBThaDdw1B2l asInUTeb9EiVfL/Zjdg5VWiF9LL7iS+9hTeVdR09vThQ/DhVbCNxVk+DtyBHsjOKifrVsYep WpRGBIAu3bK8eXtyvrw1igWTNs2wazJ71+0z2jMzbclKAyRHKU9JdN6Hkkgr2nPb561yjcB8 sIq1pFXKyO+nKy6SZYxOvHxCcjk2fkw6UmPU6/j/nQlj2lfOAgNVKuDLothIxzi8pndB8Jju KktE5HJqUUMXePkAYIxEQ0mMc8Po7tuXdejgPMwgP7x65xtfEqI0RuzbUioFltsp1jUaRwQZ MTsCeQDdjpgHsj+P2ZDeEKCbma4m6Ez/YWs4+zDm1X8uZDkZcfQlD9NldbKDJEXLIjYWo1PH hYepSffIWPyvBMBTW2W5FRjJ4vLRrJSUoEfJuPQ3vW9Y73foyo/qFoURHO48AinGPZ7PC7TF vUaNOTjKedrqHkaOcqB185ahG2had0xnFsDPlx5y In-Reply-To: <20241108143144.2f15fe35@imladris.surriel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 11/8/24 11:31, Rik van Riel wrote: > On busy multi-threaded workloads, there can be significant contention > on the mm_cpumask at context switch time. > > Reduce that contention by updating mm_cpumask lazily, setting the CPU bit > at context switch time (if not already set), and clearing the CPU bit at > the first TLB flush sent to a CPU where the process isn't running. > > When a flurry of TLB flushes for a process happen, only the first one > will be sent to CPUs where the process isn't running. The others will > be sent to CPUs where the process is currently running. So I guess it comes down to balancing: The cpumask_clear_cpu() happens on every mm switch which can be thousands of times a second. But it's _relatively_ cheap: dozens or a couple hundred cycles. with: Skipping the cpumask_clear_cpu() will cause more TLB flushes. It can cause at most one extra TLB flush for each time a process is migrated off a CPU and never returns. This is _relatively_ expensive: on the order of thousands of cycles to send and receive an IPI. Migrations are obviously the enemy here, but they're the enemy for lots of _other_ reasons too, which is a really nice property. The only thing I can think of that really worries me is some kind of forked worker model where before this patch you would have: * fork() * run on CPU A * ... migrate to CPU B * malloc()/free(), needs to flush B only * exit() and after: * fork() * run on CPU A * ... migrate to CPU B * malloc()/free(), needs to flush A+B, including IPI * exit() Where that IPI wasn't needed at *all* before. But that's totally contrived. So I think this is the kind of thing we'd want to apply to -rc1 and let the robots poke at it for a few weeks. But it does seem like a sound idea to me.