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Mon, 1 Dec 2025 18:15:24 +0000 Message-ID: <1e6bfa0c-6733-4de2-80ae-5bc08ccbf58b@intel.com> Date: Mon, 1 Dec 2025 20:15:19 +0200 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH V2 2/4] x86/insn: Add AVX-512 support to the instruction decoder To: Borislav Petkov , Masami Hiramatsu CC: , Arnaldo Carvalho de Melo , Jiri Olsa , Dan Williams , Ingo Molnar , "H. Peter Anvin" , Thomas Gleixner , Andy Lutomirski , X86 ML References: <1469003437-32706-1-git-send-email-adrian.hunter@intel.com> <1469003437-32706-3-git-send-email-adrian.hunter@intel.com> <20251130160528.GBaSxrSFwHscX3vnsB@fat_crate.local> <20251201112526.GBaS17JhPrvYGiWv3L@fat_crate.local> Content-Language: en-US From: Adrian Hunter Organization: Intel Finland Oy, Registered Address: c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo, Business Identity Code: 0357606 - 4, Domiciled in Helsinki In-Reply-To: <20251201112526.GBaS17JhPrvYGiWv3L@fat_crate.local> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: DU7P190CA0025.EURP190.PROD.OUTLOOK.COM (2603:10a6:10:550::32) To IA1PR11MB7198.namprd11.prod.outlook.com (2603:10b6:208:419::15) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: IA1PR11MB7198:EE_|MW4PR11MB6763:EE_ X-MS-Office365-Filtering-Correlation-Id: 1333edc5-2786-4a65-cf26-08de310598d7 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|366016; 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In the case of >>> new instructions, the op code map is updated accordingly. >>> >>> Also add associated Mask Instructions that are used to manipulate mask >>> registers used in AVX-512 instructions. >>> >>> 'perf tools' instruction decoder is updated in a subsequent patch. And a >>> representative set of instructions is added to the perf tools new >>> instructions test in a subsequent patch. >>> >>> Signed-off-by: Adrian Hunter >>> --- >>> arch/x86/include/asm/inat.h | 17 ++- >>> arch/x86/include/asm/insn.h | 12 +- >>> arch/x86/lib/insn.c | 18 ++- >>> arch/x86/lib/x86-opcode-map.txt | 263 +++++++++++++++++++++++------------ >>> arch/x86/tools/gen-insn-attr-x86.awk | 11 +- >>> 5 files changed, 220 insertions(+), 101 deletions(-) >>> >>> +78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) >>> +79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) >> >> This is all fine and dandy but those (ev*) flags cause the escape table to >> have INAT_EVEXONLY as a flag: >> >> const insn_attr_t inat_escape_table_1_1[INAT_OPCODE_TABLE_SIZE] = { >> ... >> >> [0x79] = INAT_MODRM | INAT_VEXOK | INAT_EVEXONLY, >> >> }; >> >> except that that opcode is not EVEX only. Intel's VMREAD and VMWRITE are *not* >> EVEX insns and AMD has there EXTRQ and INSERTQ with prefixes 66 and F2 >> respectively which are SSE4a and both are not EVEX. >> >> The VMREAD and VMWRITE decoding happens to work out by pure chance because >> those are without a prefix and the check for prefix id in >> inat_get_escape_attribute() happens to not select that escape table. >> >> So the first thing that comes to mind is excluding opcodes like 0x79 which can >> be mixed type from that inat_must_vex() enforcement...? >> >> Masami, any other ideas? > > This hack seems to do the trick. We probably should take a look at all the > insn tables and if there are more opcodes like that, to turn the mixed bool > below into a proper flag: > > > diff --git a/tools/arch/x86/lib/insn.c b/tools/arch/x86/lib/insn.c > index 1d1c57c74d1f..e3216da11a7c 100644 > --- a/tools/arch/x86/lib/insn.c > +++ b/tools/arch/x86/lib/insn.c > @@ -276,6 +276,7 @@ int insn_get_prefixes(struct insn *insn) > int insn_get_opcode(struct insn *insn) > { > struct insn_field *opcode = &insn->opcode; > + bool mixed = false; > int pfx_id, ret; > insn_byte_t op; > > @@ -348,13 +359,25 @@ int insn_get_opcode(struct insn *insn) > while (inat_is_escape(insn->attr)) { > /* Get escaped opcode */ > op = get_next(insn_byte_t, insn); > + > opcode->bytes[opcode->nbytes++] = op; > pfx_id = insn_last_prefix_id(insn); > + > + printf("%s: escaped op: 0x%x, pfx_id (insn table: none, 66, f3, f2): 0x%x, attr: 0x%x\n", > + __func__, op, pfx_id, insn->attr); > + > insn->attr = inat_get_escape_attribute(op, pfx_id, insn->attr); > + > + printf("got attr: 0x%x\n", insn->attr); > } > > - if (inat_must_vex(insn->attr)) { > + mixed = (opcode->bytes[0] == 0xf) && (opcode->bytes[1] == 0x79); > + > + printf("%s: must_vex, mixed: %d\n", __func__, mixed); > + > + if (inat_must_vex(insn->attr) && !mixed) { > /* This instruction is bad */ > + printf("%s: must_vex bad\n", __func__); > insn->attr = 0; > return -EINVAL; > } > diff --git a/tools/arch/x86/lib/x86-opcode-map.txt b/tools/arch/x86/lib/x86-opcode-map.txt > index 0139b864ceef..d059c8e63bfe 100644 > --- a/tools/arch/x86/lib/x86-opcode-map.txt > +++ b/tools/arch/x86/lib/x86-opcode-map.txt > @@ -474,7 +474,7 @@ AVXcode: 1 > # Note: Remove (v), because vzeroall and vzeroupper becomes emms without VEX. > 77: emms | vzeroupper | vzeroall > 78: VMREAD Ey,Gy | vcvttps2udq/pd2udq Vx,Wpd (evo) | vcvttsd2usi Gv,Wx (F2),(ev) | vcvttss2usi Gv,Wx (F3),(ev) | vcvttps2uqq/pd2uqq Vx,Wx (66),(ev) > -79: VMWRITE Gy,Ey | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) | EXTRQ > +79: VMWRITE Gy,Ey | EXTRQ Vo,Uo (66) | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) EXTRQ Vo,Uo (66) has a mandatory 66 prefix like vcvtps2uqq/pd2uqq Vx,Wx (66),(ev) so they end up on the same attribute table, but (ev) results in INAT_EVEXONLY which is unwanted. Changing that from (ev) to (evo) is probably all that is needed e.g. +79: VMWRITE Gy,Ey | EXTRQ Vo,Uo (66) | vcvtps2udq/pd2udq Vx,Wpd (evo) | vcvtsd2usi Gv,Wx (F2),(ev) | vcvtss2usi Gv,Wx (F3),(ev) | vcvtps2uqq/pd2uqq Vx,Wx (66),(evo)