[PATCH 0/5] ufs-exynos support for ExynosAutov920

[PATCH 0/5] ufs-exynos support for ExynosAutov920

[Sowon Na]

Hi,

This series adds support to the ufs-exynos driver for ExynosAutov920,
Samsung Automotive SoC series.
ExynosAutov920 has the UFSHCI 3.1 compliant UFS controller.

ExynosAutov920 has a different mask of UFS sharability from ExynosAutov9,
so this series provide flexible parameter for the mask.

With this series applied, UFS is functional. The Samsung KLUDG4UHYB is
tested for enumeration and I/O.

Sowon Na (5):
  phy: samsung-ufs: update calibration settings for EVT2
  dt-bindings: ufs: exynos: add ExynosAutov920 compatible string
  dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920
  scsi: ufs: exynos: add support for ExynosAutov920 SoC
  arm64: dts: exynosautov920: enable support for ufs device

 .../soc/samsung/samsung,exynos-sysreg.yaml    |   1 +
 .../bindings/ufs/samsung,exynos-ufs.yaml      |   1 +
 .../boot/dts/exynos/exynosautov920-sadk.dts   |  17 +++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |  27 ++++
 drivers/phy/samsung/phy-exynosautov920-ufs.c  |  39 ++----
 drivers/phy/samsung/phy-samsung-ufs.h         |   1 -
 drivers/ufs/host/ufs-exynos.c                 | 130 ++++++++++++++++--
 7 files changed, 180 insertions(+), 36 deletions(-)

-- 
2.45.2

[PATCH 1/5] phy: samsung-ufs: update calibration settings for EVT2

[Sowon Na]

The hardware EVT version for exynosautov920 has been updated, with EVT2
confirmed as the final production version. Accordingly, this patch updates
the UFS PHY calibration settings to match EVT2 hardware characteristics.

This ensures stable operation and optimal performance on the finalized EVT2
hardware revision.

Tested on exynosautov920 EVT2.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 drivers/phy/samsung/phy-exynosautov920-ufs.c | 39 +++++++-------------
 drivers/phy/samsung/phy-samsung-ufs.h        |  1 -
 2 files changed, 14 insertions(+), 26 deletions(-)

diff --git a/drivers/phy/samsung/phy-exynosautov920-ufs.c b/drivers/phy/samsung/phy-exynosautov920-ufs.c
index 21ef79c42f95..5ff9fc3a0615 100644
--- a/drivers/phy/samsung/phy-exynosautov920-ufs.c
+++ b/drivers/phy/samsung/phy-exynosautov920-ufs.c
@@ -12,8 +12,7 @@
 #define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CTRL_EN		BIT(0)
 #define EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS	0x5e
 
-#define EXYNOSAUTOV920_CDR_LOCK_OFFSET				0xce4
-
+#define EXYNOSAUTOV920_CAL_DONE_OFFSET				0xce0
 #define PHY_EXYNOSAUTOV920_LANE_OFFSET				0x200
 #define PHY_TRSV_REG_CFG_AUTOV920(o, v, d) \
 	PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_EXYNOSAUTOV920_LANE_OFFSET)
@@ -32,7 +31,7 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
 	PHY_TRSV_REG_CFG_AUTOV920(0x202, 0x06, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x203, 0x0a, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x204, 0x00, PWR_MODE_ANY),
-	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x10, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x205, 0x11, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x207, 0x0c, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x2e1, 0xc0, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x22d, 0xf8, PWR_MODE_ANY),
@@ -46,6 +45,7 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
 	PHY_TRSV_REG_CFG_AUTOV920(0x23e, 0x14, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x23f, 0x13, PWR_MODE_ANY),
 
+	PHY_TRSV_REG_CFG_AUTOV920(0x36e, 0x05, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x240, 0x4a, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x243, 0x40, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x244, 0x02, PWR_MODE_ANY),
@@ -76,6 +76,10 @@ static const struct samsung_ufs_phy_cfg exynosautov920_pre_init_cfg[] = {
 	PHY_TRSV_REG_CFG_AUTOV920(0x2bc, 0x06, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x2bd, 0x06, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x2be, 0x06, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2e4, 0x1a, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2ed, 0x25, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x269, 0x1a, PWR_MODE_ANY),
+	PHY_TRSV_REG_CFG_AUTOV920(0x2f4, 0x2f, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x34b, 0x01, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x34c, 0x24, PWR_MODE_ANY),
 	PHY_TRSV_REG_CFG_AUTOV920(0x34d, 0x23, PWR_MODE_ANY),
@@ -107,40 +111,25 @@ static const struct samsung_ufs_phy_cfg exynosautov920_post_pwr_hs_cfg[] = {
 
 #define DELAY_IN_US	40
 #define RETRY_CNT	100
-#define EXYNOSAUTOV920_CDR_LOCK_MASK	0x8
+#define EXYNOSAUTOV920_CAL_DONE_MASK	0x8
 
-int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane)
+static int exynosautov920_ufs_phy_wait_for_cal(struct phy *phy, u8 lane)
 {
 	struct samsung_ufs_phy *ufs_phy = get_samsung_ufs_phy(phy);
 	u32 reg, i;
 
-	struct samsung_ufs_phy_cfg cfg[4] = {
-		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x10, PWR_MODE_ANY),
-		PHY_TRSV_REG_CFG_AUTOV920(0x222, 0x18, PWR_MODE_ANY),
-		PHY_TRSV_REG_CFG_AUTOV920(0x246, 0x01, PWR_MODE_ANY),
-		END_UFS_PHY_CFG,
-	};
-
 	for (i = 0; i < RETRY_CNT; i++) {
 		udelay(DELAY_IN_US);
 
-		reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CDR_LOCK_OFFSET +
+		reg = readl(ufs_phy->reg_pma + EXYNOSAUTOV920_CAL_DONE_OFFSET +
 			(PHY_APB_ADDR(PHY_EXYNOSAUTOV920_LANE_OFFSET) * lane));
 
-		if ((reg & EXYNOSAUTOV920_CDR_LOCK_MASK)
-					== EXYNOSAUTOV920_CDR_LOCK_MASK) {
-			samsung_ufs_phy_config(ufs_phy, &cfg[2], lane);
+		if ((reg & EXYNOSAUTOV920_CAL_DONE_MASK)
+					== EXYNOSAUTOV920_CAL_DONE_MASK)
 			return 0;
-		}
-
-		udelay(DELAY_IN_US);
-
-		/* Disable and enable CDR */
-		samsung_ufs_phy_config(ufs_phy, &cfg[0], lane);
-		samsung_ufs_phy_config(ufs_phy, &cfg[1], lane);
 	}
 
-	dev_err(ufs_phy->dev, "failed to get phy cdr lock\n");
+	dev_err(ufs_phy->dev, "failed to wait for cal done\n");
 	return -ETIMEDOUT;
 }
 
@@ -164,5 +153,5 @@ const struct samsung_ufs_phy_drvdata exynosautov920_ufs_phy = {
 	.clk_list = exynosautov920_ufs_phy_clks,
 	.num_clks = ARRAY_SIZE(exynosautov920_ufs_phy_clks),
 	.cdr_lock_status_offset = EXYNOSAUTOV920_EMBEDDED_COMBO_PHY_CDR_LOCK_STATUS,
-	.wait_for_cdr = exynosautov920_ufs_phy_wait_cdr_lock,
+	.wait_for_cal = exynosautov920_ufs_phy_wait_for_cal,
 };
diff --git a/drivers/phy/samsung/phy-samsung-ufs.h b/drivers/phy/samsung/phy-samsung-ufs.h
index a28f148081d1..895741e800da 100644
--- a/drivers/phy/samsung/phy-samsung-ufs.h
+++ b/drivers/phy/samsung/phy-samsung-ufs.h
@@ -143,7 +143,6 @@ static inline void samsung_ufs_phy_ctrl_isol(
 }
 
 int samsung_ufs_phy_wait_for_lock_acq(struct phy *phy, u8 lane);
-int exynosautov920_ufs_phy_wait_cdr_lock(struct phy *phy, u8 lane);
 void samsung_ufs_phy_config(struct samsung_ufs_phy *phy,
 			    const struct samsung_ufs_phy_cfg *cfg, u8 lane);
 
-- 
2.45.2

[PATCH 2/5] dt-bindings: ufs: exynos: add ExynosAutov920 compatible string

[Sowon Na]

Add samsung,exynosautov920-ufs compatible for ExynosAutov920 SoC.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
index b4e744ebffd1..52485912d29a 100644
--- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
+++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml
@@ -19,6 +19,7 @@ properties:
       - samsung,exynos7-ufs
       - samsung,exynosautov9-ufs
       - samsung,exynosautov9-ufs-vh
+      - samsung,exynosautov920-ufs
       - tesla,fsd-ufs
 
   reg:
-- 
2.45.2

[PATCH 3/5] dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920

[Sowon Na]

Add hsi2 compatible for ExynosAutov920 ufs shareability register to
set io coherency of the ExynosAutov920 ufs.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml   | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
index d27ed6c9d61e..d8b302f97547 100644
--- a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
+++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml
@@ -30,6 +30,7 @@ properties:
               - samsung,exynos8895-fsys1-sysreg
               - samsung,exynos8895-peric0-sysreg
               - samsung,exynos8895-peric1-sysreg
+              - samsung,exynosautov920-hsi2-sysreg
               - samsung,exynosautov920-peric0-sysreg
               - samsung,exynosautov920-peric1-sysreg
               - tesla,fsd-cam-sysreg
-- 
2.45.2

[PATCH 4/5] scsi: ufs: exynos: add support for ExynosAutov920 SoC

[Sowon Na]

Add a dedicated compatible and drv_data with associated hooks for
ExynosAutov920 SoC, Samsung Autotomotive SoC series.

ExynosAutov920 has the UFSHCI 3.1 compliant UFS controller.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 drivers/ufs/host/ufs-exynos.c | 130 +++++++++++++++++++++++++++++++---
 1 file changed, 120 insertions(+), 10 deletions(-)

diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c
index 3e545af536e5..32b087099ff9 100644
--- a/drivers/ufs/host/ufs-exynos.c
+++ b/drivers/ufs/host/ufs-exynos.c
@@ -97,6 +97,10 @@
 #define UFS_EXYNOSAUTO_RD_SHARABLE	BIT(1)
 #define UFS_EXYNOSAUTO_SHARABLE		(UFS_EXYNOSAUTO_WR_SHARABLE | \
 					 UFS_EXYNOSAUTO_RD_SHARABLE)
+#define UFS_EXYNOSAUTOV920_WR_SHARABLE	BIT(3)
+#define UFS_EXYNOSAUTOV920_RD_SHARABLE	BIT(2)
+#define UFS_EXYNOSAUTOV920_SHARABLE	(UFS_EXYNOSAUTOV920_WR_SHARABLE |\
+					 UFS_EXYNOSAUTOV920_RD_SHARABLE)
 #define UFS_GS101_WR_SHARABLE		BIT(1)
 #define UFS_GS101_RD_SHARABLE		BIT(0)
 #define UFS_GS101_SHARABLE		(UFS_GS101_WR_SHARABLE | \
@@ -417,6 +421,95 @@ static int exynos7_ufs_post_pwr_change(struct exynos_ufs *ufs,
 	return 0;
 }
 
+static int exynosautov920_ufs_pre_link(struct exynos_ufs *ufs)
+{
+	struct ufs_hba *hba = ufs->hba;
+	int i;
+	u32 tx_line_reset_period, rx_line_reset_period;
+
+	rx_line_reset_period = (RX_LINE_RESET_TIME * ufs->mclk_rate)
+				/ NSEC_PER_MSEC;
+	tx_line_reset_period = (TX_LINE_RESET_TIME * ufs->mclk_rate)
+				/ NSEC_PER_MSEC;
+
+	unipro_writel(ufs, 0x5f, 0x44);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x40);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x202), 0x02);
+
+	for_each_ufs_rx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD, i),
+			       DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_CLK_PRD_EN, i), 0x0);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE2, i),
+			       (rx_line_reset_period >> 16) & 0xFF);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE1, i),
+			       (rx_line_reset_period >> 8) & 0xFF);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_RX_LINERESET_VALUE0, i),
+			       (rx_line_reset_period) & 0xFF);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x2f, i), 0x69);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x84, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x25, i), 0xf6);
+	}
+
+	for_each_ufs_tx_lane(ufs, i) {
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD, i),
+			       DIV_ROUND_UP(NSEC_PER_SEC, ufs->mclk_rate));
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_CLK_PRD_EN, i),
+			       0x02);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE2, i),
+			       (tx_line_reset_period >> 16) & 0xFF);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE1, i),
+			       (tx_line_reset_period >> 8) & 0xFF);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(VND_TX_LINERESET_PVALUE0, i),
+			       (tx_line_reset_period) & 0xFF);
+
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x04, i), 0x1);
+		ufshcd_dme_set(hba, UIC_ARG_MIB_SEL(0x7f, i), 0x0);
+	}
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x200), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_LOCAL_TX_LCC_ENABLE), 0x0);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0xa011), 0x8000);
+
+	return 0;
+}
+
+static int exynosautov920_ufs_post_link(struct exynos_ufs *ufs)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x1);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15a4), 0x3e8);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x9529), 0x0);
+
+	return 0;
+}
+
+static int exynosautov920_ufs_pre_pwr_change(struct exynos_ufs *ufs,
+					     struct ufs_pa_layer_attr *pwr)
+{
+	struct ufs_hba *hba = ufs->hba;
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(0x15d4), 0x1);
+
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_FC0PROTTIMEOUTVAL), 8064);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_TC0REPLAYTIMEOUTVAL), 28224);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(DL_AFC0REQTIMEOUTVAL), 20160);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA0), 12000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA1), 32000);
+	ufshcd_dme_set(hba, UIC_ARG_MIB(PA_PWRMODEUSERDATA2), 16000);
+
+	unipro_writel(ufs, 8064, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER0);
+	unipro_writel(ufs, 28224, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER1);
+	unipro_writel(ufs, 20160, UNIPRO_DME_POWERMODE_REQ_LOCALL2TIMER2);
+	unipro_writel(ufs, 12000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER0);
+	unipro_writel(ufs, 32000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER1);
+	unipro_writel(ufs, 16000, UNIPRO_DME_POWERMODE_REQ_REMOTEL2TIMER2);
+
+	return 0;
+}
+
 /*
  * exynos_ufs_auto_ctrl_hcc - HCI core clock control by h/w
  * Control should be disabled in the below cases
@@ -951,16 +1044,6 @@ static int exynos_ufs_phy_init(struct exynos_ufs *ufs)
 	struct phy *generic_phy = ufs->phy;
 	int ret = 0;
 
-	if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
-		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
-			&ufs->avail_ln_rx);
-		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
-			&ufs->avail_ln_tx);
-		WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
-			"available data lane is not equal(rx:%d, tx:%d)\n",
-			ufs->avail_ln_rx, ufs->avail_ln_tx);
-	}
-
 	phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
 
 	if (generic_phy->power_count) {
@@ -1065,6 +1148,16 @@ static int exynos_ufs_pre_link(struct ufs_hba *hba)
 	/* unipro */
 	exynos_ufs_config_unipro(ufs);
 
+	if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
+		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILRXDATALANES),
+			       &ufs->avail_ln_rx);
+		ufshcd_dme_get(hba, UIC_ARG_MIB(PA_AVAILTXDATALANES),
+			       &ufs->avail_ln_tx);
+		WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
+		     "available data lane is not equal(rx:%d, tx:%d)\n",
+		     ufs->avail_ln_rx, ufs->avail_ln_tx);
+	}
+
 	if (ufs->drv_data->pre_link)
 		ufs->drv_data->pre_link(ufs);
 
@@ -2183,6 +2276,21 @@ static const struct exynos_ufs_drv_data gs101_ufs_drvs = {
 	.suspend		= gs101_ufs_suspend,
 };
 
+static const struct exynos_ufs_drv_data exynosautov920_ufs_drvs = {
+	.uic_attr               = &exynos7_uic_attr,
+	.quirks                 = UFSHCD_QUIRK_SKIP_DEF_UNIPRO_TIMEOUT_SETTING,
+	.opts                   = EXYNOS_UFS_OPT_BROKEN_AUTO_CLK_CTRL |
+				  EXYNOS_UFS_OPT_SKIP_CONFIG_PHY_ATTR |
+				  EXYNOS_UFS_OPT_BROKEN_RX_SEL_IDX |
+				  EXYNOS_UFS_OPT_TIMER_TICK_SELECT,
+	.iocc_mask		= UFS_EXYNOSAUTOV920_SHARABLE,
+	.drv_init               = exynosauto_ufs_drv_init,
+	.post_hce_enable        = exynosauto_ufs_post_hce_enable,
+	.pre_link               = exynosautov920_ufs_pre_link,
+	.post_link              = exynosautov920_ufs_post_link,
+	.pre_pwr_change         = exynosautov920_ufs_pre_pwr_change,
+};
+
 static const struct of_device_id exynos_ufs_of_match[] = {
 	{ .compatible = "google,gs101-ufs",
 	  .data	      = &gs101_ufs_drvs },
@@ -2192,6 +2300,8 @@ static const struct of_device_id exynos_ufs_of_match[] = {
 	  .data	      = &exynosauto_ufs_drvs },
 	{ .compatible = "samsung,exynosautov9-ufs-vh",
 	  .data	      = &exynosauto_ufs_vh_drvs },
+	{ .compatible = "samsung,exynosautov920-ufs",
+	  .data       = &exynosautov920_ufs_drvs },
 	{ .compatible = "tesla,fsd-ufs",
 	  .data       = &fsd_ufs_drvs },
 	{},
-- 
2.45.2

[PATCH 5/5] arm64: dts: exynosautov920: enable support for ufs device

[Sowon Na]

The exynosautov920 uses v3.1 UFS device.
Add ufs node for ExynosAutov920 SoC.
And enable ufs_phy and ufs devices with ufs_fixed_vcc_reg regulator for
ExynosAutov920 SADK.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
---
 .../boot/dts/exynos/exynosautov920-sadk.dts   | 17 ++++++++++++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi | 27 +++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
index a397f068ed53..f979cc1ae6a1 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
+++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
@@ -52,6 +52,14 @@ memory@80000000 {
 		      <0x8 0x80000000 0x1 0xfba00000>,
 		      <0xa 0x00000000 0x2 0x00000000>;
 	};
+
+	ufs_fixed_vcc_reg: regulator-0 {
+		compatible = "regulator-fixed";
+		regulator-name = "ufs-vcc";
+		gpio = <&gpg3 2 GPIO_ACTIVE_HIGH>;
+		regulator-boot-on;
+		enable-active-high;
+	};
 };
 
 &pinctrl_alive {
@@ -83,6 +91,15 @@ &usi_0 {
 	status = "okay";
 };
 
+&ufs_0 {
+	status = "okay";
+	vcc-supply = <&ufs_fixed_vcc_reg>;
+};
+
+&ufs_0_phy {
+	status = "okay";
+};
+
 &xtcxo {
 	clock-frequency = <38400000>;
 };
diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index 0fdf2062930a..f787c28fb0d5 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -1426,6 +1426,12 @@ cmu_hsi2: clock-controller@16b00000 {
 				      "ethernet";
 		};
 
+		syscon_hsi2: syscon@16c00000 {
+			compatible = "samsung,exynosautov920-hsi2-sysreg",
+				     "syscon";
+			reg = <0x16c00000 0x800>;
+		};
+
 		pinctrl_hsi2: pinctrl@16c10000 {
 			compatible = "samsung,exynosautov920-pinctrl";
 			reg = <0x16c10000 0x10000>;
@@ -1438,6 +1444,27 @@ pinctrl_hsi2ufs: pinctrl@16d20000 {
 			interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		ufs_0: ufs@16e00000 {
+			compatible = "samsung,exynosautov920-ufs";
+			reg = <0x16e00000 0x100>,
+			      <0x16e01100 0x400>,
+			      <0x16e80000 0x8000>,
+			      <0x16d08000 0x800>;
+			reg-names = "hci", "vs_hci", "unipro", "ufsp";
+			interrupts = <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cmu_hsi2 CLK_MOUT_HSI2_UFS_EMBD_USER>,
+				 <&cmu_hsi2 CLK_MOUT_HSI2_NOC_UFS_USER>;
+			clock-names = "core_clk", "sclk_unipro_main";
+			freq-table-hz = <0 0>, <0 0>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&ufs_rst_n &ufs_refclk_out>;
+			phys = <&ufs_0_phy>;
+			phy-names = "ufs-phy";
+			samsung,sysreg = <&syscon_hsi2 0x710>;
+			dma-coherent;
+			status = "disabled";
+		};
+
 		ufs_0_phy: phy@16e04000 {
 			compatible = "samsung,exynosautov920-ufs-phy";
 			reg = <0x16e04000 0x4000>;
-- 
2.45.2

[PATCH 0/5] ufs-exynos support for ExynosAutov920

[Sowon Na]

Hi,

This series adds support to the ufs-exynos driver for ExynosAutov920,
Samsung Automotive SoC series.
ExynosAutov920 has the UFSHCI 3.1 compliant UFS controller.

ExynosAutov920 has a different mask of UFS sharability from ExynosAutov9,
so this series provide flexible parameter for the mask.

With this series applied, UFS is functional. The Samsung KLUDG4UHYB is
tested for enumeration and I/O.

Sowon Na (5):
  phy: samsung-ufs: update calibration settings for EVT2
  dt-bindings: ufs: exynos: add ExynosAutov920 compatible string
  dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920
  scsi: ufs: exynos: add support for ExynosAutov920 SoC
  arm64: dts: exynosautov920: enable support for ufs device

 .../soc/samsung/samsung,exynos-sysreg.yaml    |   1 +
 .../bindings/ufs/samsung,exynos-ufs.yaml      |   1 +
 .../boot/dts/exynos/exynosautov920-sadk.dts   |  17 +++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi |  27 ++++
 drivers/phy/samsung/phy-exynosautov920-ufs.c  |  39 ++----
 drivers/phy/samsung/phy-samsung-ufs.h         |   1 -
 drivers/ufs/host/ufs-exynos.c                 | 130 ++++++++++++++++--
 7 files changed, 180 insertions(+), 36 deletions(-)

-- 
2.45.2

Re: [PATCH 5/5] arm64: dts: exynosautov920: enable support for ufs device

[Krzysztof Kozlowski]

On 02/07/2025 03:33, Sowon Na wrote:
> The exynosautov920 uses v3.1 UFS device.
> Add ufs node for ExynosAutov920 SoC.
> And enable ufs_phy and ufs devices with ufs_fixed_vcc_reg regulator for
> ExynosAutov920 SADK.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
>  .../boot/dts/exynos/exynosautov920-sadk.dts   | 17 ++++++++++++
>  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 27 +++++++++++++++++++
>  2 files changed, 44 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
> index a397f068ed53..f979cc1ae6a1 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts
> @@ -52,6 +52,14 @@ memory@80000000 {
>  		      <0x8 0x80000000 0x1 0xfba00000>,
>  		      <0xa 0x00000000 0x2 0x00000000>;
>  	};
> +
> +	ufs_fixed_vcc_reg: regulator-0 {


This should be somehow related to real name. Schematics don't call
regulators "fixed" or "non-fixed", which makes me think that you forgot
to implement PMIC.

Best regards,
Krzysztof

Re: [PATCH 2/5] dt-bindings: ufs: exynos: add ExynosAutov920 compatible string

[Krzysztof Kozlowski]

On Wed, Jul 02, 2025 at 10:33:08AM +0900, Sowon Na wrote:
> Add samsung,exynosautov920-ufs compatible for ExynosAutov920 SoC.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
>  Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml | 1 +
>  1 file changed, 1 insertion(+)

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 3/5] dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920

[Krzysztof Kozlowski]

On Wed, Jul 02, 2025 at 10:33:09AM +0900, Sowon Na wrote:
> Add hsi2 compatible for ExynosAutov920 ufs shareability register to
> set io coherency of the ExynosAutov920 ufs.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
>  .../devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml   | 1 +
>  1 file changed, 1 insertion(+)
> 

You combined in this patchset three subsystems. That's not helping...

Best regards,
Krzysztof

Re: (subset) [PATCH 3/5] dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920

[Krzysztof Kozlowski]

On Wed, 02 Jul 2025 10:33:09 +0900, Sowon Na wrote:
> Add hsi2 compatible for ExynosAutov920 ufs shareability register to
> set io coherency of the ExynosAutov920 ufs.
> 
> 

Applied, thanks!

[3/5] dt-bindings: soc: samsung: exynos-sysreg: add hsi2 for ExynosAutov920
      https://git.kernel.org/krzk/linux/c/687d974a218a719f7e729bef9c498ec36f18115e

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

RE: [PATCH 1/5] phy: samsung-ufs: update calibration settings for EVT2

[Alim Akhtar]

Hi Sowon, 

> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Wednesday, July 2, 2025 7:03 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH 1/5] phy: samsung-ufs: update calibration settings for EVT2
> 
> The hardware EVT version for exynosautov920 has been updated, with EVT2
> confirmed as the final production version. Accordingly, this patch updates the
> UFS PHY calibration settings to match EVT2 hardware characteristics.
> 
This patch does more then what is mentioned here, 
please update the commit with all the changes so that we understand why the changes was done. 
.
.
.[snip]
> -#define EXYNOSAUTOV920_CDR_LOCK_OFFSET
> 	0xce4
> -
> +#define EXYNOSAUTOV920_CAL_DONE_OFFSET
> 	0xce0
Any reason for not using CRD lock and using Cal Done? 

RE: [PATCH 2/5] dt-bindings: ufs: exynos: add ExynosAutov920 compatible string

[Alim Akhtar]

> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Wednesday, July 2, 2025 7:03 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH 2/5] dt-bindings: ufs: exynos: add ExynosAutov920
> compatible string
> 
> Add samsung,exynosautov920-ufs compatible for ExynosAutov920 SoC.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

RE: [PATCH 4/5] scsi: ufs: exynos: add support for ExynosAutov920 SoC

[Alim Akhtar]

> -----Original Message-----
> From: Sowon Na <sowon.na@samsung.com>
> Sent: Wednesday, July 2, 2025 7:03 AM
> To: robh@kernel.org; krzk@kernel.org; conor+dt@kernel.org;
> vkoul@kernel.org; alim.akhtar@samsung.com; kishon@kernel.org
> Cc: krzk+dt@kernel.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org; linux-samsung-soc@vger.kernel.org;
> sowon.na@samsung.com
> Subject: [PATCH 4/5] scsi: ufs: exynos: add support for ExynosAutov920 SoC
> 
> Add a dedicated compatible and drv_data with associated hooks for
> ExynosAutov920 SoC, Samsung Autotomotive SoC series.
> 
> ExynosAutov920 has the UFSHCI 3.1 compliant UFS controller.
> 
> Signed-off-by: Sowon Na <sowon.na@samsung.com>
> ---
>  drivers/ufs/host/ufs-exynos.c | 130
> +++++++++++++++++++++++++++++++---
>  1 file changed, 120 insertions(+), 10 deletions(-)
> 
[snip]

>  	struct phy *generic_phy = ufs->phy;
>  	int ret = 0;
> 
> -	if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
> -		ufshcd_dme_get(hba,
> UIC_ARG_MIB(PA_AVAILRXDATALANES),
> -			&ufs->avail_ln_rx);
> -		ufshcd_dme_get(hba,
> UIC_ARG_MIB(PA_AVAILTXDATALANES),
> -			&ufs->avail_ln_tx);
> -		WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
> -			"available data lane is not equal(rx:%d, tx:%d)\n",
> -			ufs->avail_ln_rx, ufs->avail_ln_tx);
> -	}
> -

Why you are moving these changes from exynos_ufs_phy_init() to exynos_ufs_pre_link()? 
If at all this is needed, this need to be a separate patch, not related to adding exynosautov920 support. 

>  	phy_set_bus_width(generic_phy, ufs->avail_ln_rx);
> 
>  	if (generic_phy->power_count) {
> @@ -1065,6 +1148,16 @@ static int exynos_ufs_pre_link(struct ufs_hba
> *hba)
>  	/* unipro */
>  	exynos_ufs_config_unipro(ufs);
> 
> +	if (ufs->avail_ln_rx == 0 || ufs->avail_ln_tx == 0) {
> +		ufshcd_dme_get(hba,
> UIC_ARG_MIB(PA_AVAILRXDATALANES),
> +			       &ufs->avail_ln_rx);
> +		ufshcd_dme_get(hba,
> UIC_ARG_MIB(PA_AVAILTXDATALANES),
> +			       &ufs->avail_ln_tx);
> +		WARN(ufs->avail_ln_rx != ufs->avail_ln_tx,
> +		     "available data lane is not equal(rx:%d, tx:%d)\n",
> +		     ufs->avail_ln_rx, ufs->avail_ln_tx);
> +	}
> +