From: Grygorii Strashko <grygorii.strashko@ti.com>
To: David Miller <davem@davemloft.net>
Cc: <netdev@vger.kernel.org>, <mugunthanvnm@ti.com>, <nsekhar@ti.com>,
<linux-kernel@vger.kernel.org>, <linux-omap@vger.kernel.org>,
<ivan.khoronzhuk@linaro.org>
Subject: Re: [PATCH 1/7] net: ethernet: ti: cpdma: am437x: allow descs to be plased in ddr
Date: Mon, 5 Dec 2016 11:57:42 -0600 [thread overview]
Message-ID: <1fbfc83f-c48b-45da-6bc3-d37b2bb129b6@ti.com> (raw)
In-Reply-To: <20161203.153419.482900037601991931.davem@davemloft.net>
On 12/03/2016 02:34 PM, David Miller wrote:
> From: Grygorii Strashko <grygorii.strashko@ti.com>
> Date: Thu, 1 Dec 2016 17:34:26 -0600
>
>> @@ -167,10 +167,10 @@ static struct cpdma_control_info controls[] = {
>>
>> /* various accessors */
>> #define dma_reg_read(ctlr, ofs) __raw_readl((ctlr)->dmaregs + (ofs))
>> -#define chan_read(chan, fld) __raw_readl((chan)->fld)
>> +#define chan_read(chan, fld) readl((chan)->fld)
>> #define desc_read(desc, fld) __raw_readl(&(desc)->fld)
>> #define dma_reg_write(ctlr, ofs, v) __raw_writel(v, (ctlr)->dmaregs + (ofs))
>> -#define chan_write(chan, fld, v) __raw_writel(v, (chan)->fld)
>> +#define chan_write(chan, fld, v) writel(v, (chan)->fld)
>> #define desc_write(desc, fld, v) __raw_writel((u32)(v), &(desc)->fld)
>
> Unless you want to keep running into subtle errors all over the
> place wrt. register vs. memory write ordering, I strong suggest
> you use strongly ordered readl/writel for all register accesses.
>
> I see no tangible, worthwhile, advantage to using these relaxed
> ordering primitives. The only result is potential bugs.
>
> People who use the relaxed ordering primitives properly are only
> doing so in extremely carefully coded sequences where a series
> of writes has no dependency on main memory operations and is
> explicitly completed with a barrier operation such as a read
> back of a register in the same device.
>
> That's not at all what is going on here, instead the driver is wildly
> using relaxed ordered register accesses for basically everything.
> This is extremely unwise and it's why you ran into this bug in the
> first place.
>
> Therefore, I absolutely require that you fix this by eliminating
> any and all usese of relaxed ordering I/O accessors in this driver.
Thanks for your comments - that's what I've tried first, but that decided
to find out minimal change which still works.
I'll update it.
--
regards,
-grygorii
next prev parent reply other threads:[~2016-12-05 17:57 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-01 23:34 [PATCH 0/7] net: ethernet: ti: cpsw: support placing CPDMA descriptors into DDR Grygorii Strashko
2016-12-01 23:34 ` [PATCH 1/7] net: ethernet: ti: cpdma: am437x: allow descs to be plased in ddr Grygorii Strashko
2016-12-03 20:34 ` David Miller
2016-12-05 17:57 ` Grygorii Strashko [this message]
2016-12-01 23:34 ` [PATCH 2/7] net: ethernet: ti: cpdma: fix desc re-queuing Grygorii Strashko
2016-12-02 11:03 ` Ivan Khoronzhuk
2016-12-02 16:45 ` Grygorii Strashko
2016-12-02 23:28 ` Ivan Khoronzhuk
2016-12-05 18:22 ` Grygorii Strashko
2016-12-01 23:34 ` [PATCH 3/7] net: ethernet: ti: cpdma: minimize number of parameters in cpdma_desc_pool_create/destroy() Grygorii Strashko
2016-12-01 23:34 ` [PATCH 4/7] net: ethernet: ti: cpdma: use devm_ioremap Grygorii Strashko
2016-12-01 23:34 ` [PATCH 5/7] Documentation: DT: net: cpsw: allow to specify descriptors pool size Grygorii Strashko
2016-12-02 11:28 ` Ivan Khoronzhuk
2016-12-02 17:21 ` Grygorii Strashko
2016-12-07 19:41 ` Grygorii Strashko
2016-12-02 17:22 ` Grygorii Strashko
2016-12-03 0:37 ` Ivan Khoronzhuk
2016-12-01 23:34 ` [PATCH 6/7] net: ethernet: ti: cpsw: add support for descs_pool_size dt property Grygorii Strashko
2016-12-01 23:34 ` [PATCH 7/7] Documentation: DT: net: cpsw: remove no_bd_ram property Grygorii Strashko
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