Re: [RFC PATCH 06/12] perf: Support extension of sample_regs

[Dave Hansen <dave.hansen@intel.com>]

On 6/18/25 06:52, Liang, Kan wrote:
> On 2025-06-18 9:30 a.m., Peter Zijlstra wrote:
>> On Wed, Jun 18, 2025 at 06:10:20AM -0400, Liang, Kan wrote:
>>
>>> Maybe we should use a mask to replace the nr_vectors.
>>> Because Dave mentioned that the XSAVES may fail.
>> XSAVE is a pain in the arse :/
>>
>>> PERF_SAMPLE_SIMD_REGS := {
>>> 	u64 vectors_mask;
>>> 	u16 vector_length;
>>> 	u64 pred_mask;
>>> 	u16 pred_length;
>> That is not u64 aligned...
> I didn't know we have the alignment requirement for the output.
> If so,
> 
> PERF_SAMPLE_SIMD_REGS := {
> 	u64 vectors_mask;
> 	u64 pred_mask;
> 	u64 vector_length:16,
> 	    pred_length:16,
> 	    reserved:32;
> 	u64 data[];
> }

There are three different in-memory register layouts that are in play:

 * The "sane" format that, for instance, packs all of the bytes of ZMM0
   in memory next to each other, like you've been talking about in the
   thread.
 * The PEBS XER Record Format. There's a 16-byte header before the real
   registers start. The registers have an XSAVE-style split where (for
   instance) ZMM0 is in three pieces.
 * The XSAVE{,C,S,OPT} format. There's a 160-byte of "x87 state" gunk at
   the beginning that's not read or written, then XMM[0-16], then 112
   bytes of space, then X{STATE,COMP}_BV, a 48 byte gap, then the AVX
   state. There's a bunch of space in the first 576 bytes.

XSAVE can't write the first two formats at *all*, although the PEBS and
XSAVE formats are the same for AVX and later.

So one of the immediate questions is whether we want to expose the XSAVE
format as part of the perf ABI. I'm _assuming_ that the PEBS format is
going to be exposed to userspace, so should we expose XSAVE or munge it
into one of the other two formats?

If software is going to munge the XSAVE format, then you don't have to
worry about alignment because you'd save it to some probably per-cpu
64-byte-aligned buffer and then munge it into the unaligned
PERF_SAMPLE_SIMD_REGS above.